[MOS-1011] Fix frequency switching stability

Multiple fixes of clock switching related
stability issues:
* added RC oscillator hysteresis as in NXP example;
* changed DCDC converter config;
* configure PLL2 to be able to run on any CPU
frequency level;
* added switching to 1.275V (overdrive) voltage
when applying any clock change above 12MHz as
well as LDO or bandgap switching, as done in
Mbed OS' lpm.c for RT1050;
* changed BMCR AXI queues weighs for SDRAM
in JLink scripts to disable operations
reordering, as it is known to cause data
integrity issues;
* extracted some code to separate files;
* smaller or bigger code cleanups.

module-sys/SystemManager/cpu/algorithm/FrequencyStepping.cpp

@@ -1,4 +1,4 @@
-// Copyright (c) 2017-2022, Mudita Sp. z.o.o. All rights reserved.
+// Copyright (c) 2017-2023, Mudita Sp. z.o.o. All rights reserved.
 // For licensing, see https://github.com/mudita/MuditaOS/LICENSE.md
 
 #include "FrequencyStepping.hpp"
@@ -23,9 +23,7 @@ namespace sys::cpu
         case bsp::CpuFrequencyMHz::Level_3:
             return bsp::CpuFrequencyMHz::Level_2;
         case bsp::CpuFrequencyMHz::Level_2:
-            [[fallthrough]];
         case bsp::CpuFrequencyMHz::Level_1:
-            [[fallthrough]];
         case bsp::CpuFrequencyMHz::Level_0:
             return profile.minimalFrequency;
         }