Add init eMMC pins to make sure that the pins
are configured in debug mode. If we run a debug mode
the 1st bootloader is not run so the pins may have
incorrect config. Added config also for Pure.
Bump ecoboot version with this same fix.
The battery charger worker had only ~10% free
stack size so it was a possibility to stack overflow.
After increasing the stack by 512 bytes the worker
has ~40% free stack space.
* Fix of the issue that choosing French
or Spanish as a system language
resulted in no input language selected.
* Added keyboard input parser unit
tests for French and Spanish input
maps.
* Minor cleanups.
* Fixed initial RTWDOG config procedure, which
put watchdog module in some non-deterministic
state due to not waiting after unlock request
and config change, what prevented the watchdog
to be reconfigured later in the OS.
* Configured RTWDOG to continue running in
WFI to prevent potential freezes caused by
CPU not being woken up by periodic RTC
interrupt.
* Added mechanism enabling CPU to
enter WFI mode when the OS is
in idle, what results in large
power consumption reduction.
* Added mechanism to switch SDRAM to
self-refresh mode before entering
WFI, what resulted in further power
consumption reduction.
* Fix of the issue that source clock for PWM
module was improperly assumed to be derived
from AHB_CLK, while in reality it is
derived from IPG_CLK, what resulted in
module generating signal with 4 times
lower frequency than the configured
one.
* Cleanups.
To allow the automation of gathering logs and swapping out OS images during tests a MSC reboot
endpoint was added. Together with a change to ecoboot, this allows the sending of a "reboot to
MSC" command. The deivce will then reboot and enter MSC mode.
According to the newest fsl library the LPSPI_Reset function
shouldn't be invoked in LPSPI_MasterInit function.
As a result, the LPSPI module can't work after calling this API.
If the display returns the error the driver could invoke
EinkPowerDown function recursively which causes a crash.
* Adding document describing how to use logger
* Adjusting logs to follow a new guide
* Change order in log header:
line number is now before function name
Multiple fixes of clock switching related
stability issues:
* added RC oscillator hysteresis as in NXP example;
* changed DCDC converter config;
* configure PLL2 to be able to run on any CPU
frequency level;
* added switching to 1.275V (overdrive) voltage
when applying any clock change above 12MHz as
well as LDO or bandgap switching, as done in
Mbed OS' lpm.c for RT1050;
* changed BMCR AXI queues weighs for SDRAM
in JLink scripts to disable operations
reordering, as it is known to cause data
integrity issues;
* extracted some code to separate files;
* smaller or bigger code cleanups.
* Added extended logging to Pure's charger driver.
* Removed redundant handling of INOKB pin
interrupt - charger is configured to provide
the same interrupt via INTB pin.
* Minor code cleanup.
Optimized power management strategy used by
ServiceAudio:
* changed minimum CPU frequency from 528MHz to 264MHz;
* added switching to 24MHz when operation active,
but paused;
* minor cleanup in several places.
If the CPU fails during changing the frequency
the device can stuck in SNVS mode.
So the CPU frequency is checked and if
the frequency is wrong the CPU doesn’t enter SNVS mode.
The watchdog should restart the CPU.
Added info about product, OS version and
commit hash to crashdump filename to
simplify analysis of the crashdumps
without corresponding logs available.
The secure RTC can lock and the clock is not updated.
To prevent this situation we reset LP registers (except for
timestamps and alarms) and clear the LVD flag. Then we
enable again LP SRTC.
When the button is pressed/released we get an interrupt
which falls or rises edge. We read the gpio state a bit
later so in case of debouncing we can register
the wrong pin state.
After the debounce interval the state is stable.
Added mechanism that stores address of last
executed instruction before RTWDOG timeout
to enable some basic debugging in such cases,
as such resets do not create crashdumps and
leave no information in logs.
Added extended statistics to help track potential memory leaks:
* used user heap size per task
* number of successful allocations
* number of successful frees
Next part of Harmony random resets fixes:
* added RC OSC startup delay as in newest lpm.c;
* changed order of clock source, oscillator and
LDO switching;
* removed connecting internal DCDC load resistor,
as it is only required to speed up converter
startup after it was turned off completely;
* changed DCDC operation mode to continuous
conduction;
* set low VDD_SOC_IN voltage back to 950mV as
suggested in RM.
* added switching DCDC converter mode to
discontinuous conduction for two lowest CPU
clock frequencies, as using CCM mode resulted
in very high current consumption that would
shorten Harmony's life on battery
significantly.
* Switching VDD_SOC_IN only after PLL2 is turned off.
* Weak LDO stabilization delay.
* Removed switching to 1.275V before frequency change.
* Cleanups in LDO switching.
* Removed switching PeriphClk2Div for fCPU <= 24MHz,
using AhbDiv instead.
* Removed log from _exit that caused logger mutex deadlock
Fixed file access via MTP even when phone is not unlocked.
Now access is granted when the phone is unlocked by the user entering
a passcode. If the phone is not passcode protected (passcode is nor set)
then access to the files is always possible via MTP.
