Multiple fixes of clock switching related
stability issues:
* added RC oscillator hysteresis as in NXP example;
* changed DCDC converter config;
* configure PLL2 to be able to run on any CPU
frequency level;
* added switching to 1.275V (overdrive) voltage
when applying any clock change above 12MHz as
well as LDO or bandgap switching, as done in
Mbed OS' lpm.c for RT1050;
* changed BMCR AXI queues weighs for SDRAM
in JLink scripts to disable operations
reordering, as it is known to cause data
integrity issues;
* extracted some code to separate files;
* smaller or bigger code cleanups.
