mirror of
https://github.com/mudita/MuditaOS.git
synced 2026-04-18 06:00:30 -04:00
* Fix of the issue that source clock for PWM module was improperly assumed to be derived from AHB_CLK, while in reality it is derived from IPG_CLK, what resulted in module generating signal with 4 times lower frequency than the configured one. * Cleanups.