mirror of
https://github.com/mudita/MuditaOS.git
synced 2026-02-06 04:12:02 -05:00
54bf8311b0
Now the system uses 2.14.0 version. Add only necessary drivers: - pit - pmu - rtwdog - snvs_hp - snvs_lp - src - trng - wdog - gpio - gpt - lpi2c - lpuart - lpuart_edma - common - common_arm - dmamux - edma - flexram - flexram_allocate - clock - cache - CMSIS - dcp - iomuxc Changed speed of the USDHC clock from ~109MHz to ~81MHz. Also changed bus timing from kMMC_HighSpeedTiming to kMMC_HighSpeed200Timing for better efficiency.
274 lines
11 KiB
C++
274 lines
11 KiB
C++
#include "bsp.hpp"
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#include "board.h"
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extern "C"
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{
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#include "fsl_common.h"
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#include "fsl_dcdc.h"
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#include "fsl_snvs_hp.h"
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#include "fsl_snvs_lp.h"
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#include "board/pin_mux.h"
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#if LOG_LUART_ENABLED
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#include "fsl_lpuart.h"
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#endif
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}
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#include "chip.hpp"
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#include "board/irq_gpio.hpp"
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#include "board/brownout.hpp"
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#include <board/debug_console.hpp>
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#include <log/log.hpp>
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#include <magic_enum.hpp>
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extern std::uint32_t __sdram_cached_start[];
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extern "C"
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{
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std::uint32_t boot_reason_get_raw()
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{
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return SNVS->LPGPR[0];
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}
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void boot_reason_set_raw(std::uint32_t raw)
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{
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SNVS->LPGPR[0] = raw;
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}
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}
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namespace bsp
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{
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namespace
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{
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volatile RebootState rebootProgress{RebootState::None};
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struct PlatformExitObject
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{
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void (*func)();
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};
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unsigned short registeredObjectsCount = 0;
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constexpr auto maxRegisteredObjectsCount = 16U;
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PlatformExitObject exitObjects[maxRegisteredObjectsCount];
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void call_platform_exit_functions()
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{
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while (registeredObjectsCount > 0) {
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exitObjects[--registeredObjectsCount].func();
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}
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}
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/* MPU configuration. */
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void BOARD_ConfigMPU()
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{
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
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SCB_DisableICache();
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}
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
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SCB_DisableDCache();
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
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* SubRegionDisable, Size) API in core_cm7.h. param DisableExec Instruction access (XN) disable
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* bit,0=instruction fetches enabled, 1=instruction fetches disabled. param AccessPermission Data access
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* permissions, allows you to configure read/write access for User and Privileged mode. Use MACROS defined
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* in core_cm7.h:
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* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO Combine
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* TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. TypeExtField
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* IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache 0 x 0
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* 0 Strongly Ordered shareable 0 x 0 1 Device
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* shareable 0 0 1 0 Normal not shareable Outer
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* and inner write through no write allocate 0 0 1 1 Normal not
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* shareable Outer and inner write back no write allocate 0 1 1 0 Normal
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* shareable Outer and inner write through no write allocate 0 1 1 1
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* Normal shareable Outer and inner write back no write allocate 1 0 0 0
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* Normal not shareable outer and inner noncache 1 1 0 0 Normal
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* shareable outer and inner noncache 1 0 1 1 Normal not shareable
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* outer and inner write back write/read acllocate 1 1 1 1 Normal shareable
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* outer and inner write back write/read acllocate 2 x 0 0 Device not shareable Above are normal
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* use settings, if your want to see more details or want to config different inner/outter cache policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf> param
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* SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. param Size
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* Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
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*/
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/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Setting Memory with Normal type, not shareable, outer/inner write back. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
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#else
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/* Setting Memory with Device type, not shareable, non-cacheable. */
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// TODO: MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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// TODO: MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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#endif
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/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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// CPU doesn't use cache when accessing TCM memories
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/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
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// OCRAM configured as non-cached segment
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/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64KB);
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back
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* BOARD_SDRAM_TEXT
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*/
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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#if defined(HW_SDRAM_64_MB) && (HW_SDRAM_64_MB == 1)
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
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#else
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
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#endif
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/* The define sets the cacheable memory to shareable,
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* this suggestion is referred from chapter 2.2.1 Memory regions,
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* types and attributes in Cortex-M7 Devices, Generic User Guide */
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#if defined(SDRAM_IS_SHAREABLE)
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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#else
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/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back
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* BOARD_SDRAM_HEAP
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*/
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MPU->RBAR = ARM_MPU_RBAR(9, reinterpret_cast<std::uintptr_t>(__sdram_cached_start));
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#if defined(HW_SDRAM_64_MB) && (HW_SDRAM_64_MB == 1)
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
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#else
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
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#endif // HW_SDRAM_64_MB
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#endif // SDRAM_IS_SHAREABLE
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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} // namespace
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void board_init()
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{
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PINMUX_InitBootPins();
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BOARD_InitBootClocks();
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BOARD_ConfigMPU();
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board::initDebugConsole();
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Brownout_init();
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irq_gpio_Init();
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SNVS_LP_Init(SNVS);
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SNVS_HP_Init(SNVS);
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SNVS_HP_ChangeSSMState(SNVS);
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// Default flag set on start in non-volatile memory to detect boot fault
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// SNVS->LPGPR[0] = rebootCode::rebootFailedToBoot;
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// TODO: Here we can implement boot-time fail detection
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PrintSystemClocks();
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clearAndPrintBootReason();
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board_configure();
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if (SNVS->LPGPR[1] != 0) {
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LOG_INFO("Device seems to have been reset by RTWDOG! Last instruction address: 0x%08lX", SNVS->LPGPR[1]);
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SNVS->LPGPR[1] = 0;
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}
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}
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//! Board PowerOff function by power cutoff
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void board_power_off()
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{
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rebootProgress = RebootState::Poweroff;
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}
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//! Board reboot by the SNVS code
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void board_restart()
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{
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rebootProgress = RebootState::Reboot;
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}
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int register_exit_function(void (*func)())
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{
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if (registeredObjectsCount >= sizeof(exitObjects)) {
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return -ENOMEM;
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}
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exitObjects[registeredObjectsCount].func = func;
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++registeredObjectsCount;
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return 0;
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}
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extern "C" void _platform_exit(void)
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{
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call_platform_exit_functions();
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bsp::board_exit(rebootProgress);
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}
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/* This function is invoked at the end of the SystemInit() function.
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* This can be used when an application specific code needs
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* to be called as close to the reset entry as possible.
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* NOTE: No global r/w variables can be used in this hook function because the
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* initialization of these variables happens after this function.
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*/
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extern "C" void SystemInitHook(void)
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{
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#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
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if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
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SCB_EnableDCache();
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}
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#endif
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// Disable WDOGx watchdogs timers
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if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) {
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WDOG1->WCR &= ~(uint16_t)WDOG_WCR_WDE_MASK;
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}
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if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) {
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WDOG2->WCR &= ~(uint16_t)WDOG_WCR_WDE_MASK;
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}
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#if (!DISABLE_WDOG)
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/* Perform preliminary RTWDOG configuration */
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/* Write RTWDOG update key to unlock */
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if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) {
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RTWDOG->CNT = 0xD928C520U;
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}
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else {
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RTWDOG->CNT = 0xC520;
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RTWDOG->CNT = 0xD928;
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}
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/* Set timeout value to 16s (assuming 128Hz clock - 32.768kHz from LPO_CLK, with 256 prescaler) */
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RTWDOG->TOVAL = 16 * 128;
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/* Enable RTWDOG, set 256 clock prescaler and allow configuration updates, wait until config is applied */
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RTWDOG->CS |= (RTWDOG_CS_EN_MASK | RTWDOG_CS_PRES_MASK | RTWDOG_CS_UPDATE_MASK);
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while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0U) {}
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#endif // (DISABLE_WDOG)
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}
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} // namespace bsp
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