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https://github.com/mudita/MuditaOS.git
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3cbbeff551
Multiple fixes of clock switching related stability issues: * added RC oscillator hysteresis as in NXP example; * changed DCDC converter config; * configure PLL2 to be able to run on any CPU frequency level; * added switching to 1.275V (overdrive) voltage when applying any clock change above 12MHz as well as LDO or bandgap switching, as done in Mbed OS' lpm.c for RT1050; * changed BMCR AXI queues weighs for SDRAM in JLink scripts to disable operations reordering, as it is known to cause data integrity issues; * extracted some code to separate files; * smaller or bigger code cleanups.
71 lines
2.2 KiB
C++
71 lines
2.2 KiB
C++
// Copyright (c) 2017-2023, Mudita Sp. z.o.o. All rights reserved.
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// For licensing, see https://github.com/mudita/MuditaOS/LICENSE.md
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#include "RT1051DriverPLL2.hpp"
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#include "board/rt1051/bsp/lpm/ClockState.hpp"
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#include "board/rt1051/bsp/lpm/CpuFreqLPM.hpp"
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#include "board/rt1051/bsp/lpm/Bandgap.hpp"
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#include "board/rt1051/bsp/lpm/LDO.hpp"
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#include "board/rt1051/bsp/lpm/DCDC.hpp"
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namespace
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{
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inline std::uint32_t getCurrentVDDRunVoltage()
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{
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return (DCDC->REG3 & DCDC_REG3_TRG_MASK);
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}
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} // namespace
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namespace drivers
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{
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RT1051DriverPLL2::RT1051DriverPLL2() noexcept
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{
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if (!IsPLL2Enabled()) {
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/* Check if switching conditions already met */
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const auto isCurrentVoltageOverdrive = (getCurrentVDDRunVoltage() >= bsp::VDDRun_1275_mV);
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if (!isCurrentVoltageOverdrive) {
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bsp::dcdc::SwitchToOverdriveConfig();
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}
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/* Switch to regular bandgap */
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bsp::bandgap::SwitchToRegularMode();
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/* Switch to regular LDO */
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bsp::ldo::SwitchToRegularMode();
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/* Switch back to regular config */
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if (!isCurrentVoltageOverdrive) {
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bsp::dcdc::SwitchToRegularConfig();
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}
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/* Enable PLL2 */
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clkPLL2setup(CLK_ENABLE);
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}
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}
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RT1051DriverPLL2::~RT1051DriverPLL2() noexcept
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{
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if ((CLOCK_GetMux(kCLOCK_SemcMux) == SemcMuxPeripheralClock) && !bsp::IsClockEnabled(kCLOCK_Lpspi1) &&
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!bsp::IsClockEnabled(kCLOCK_Lpspi2) && !bsp::IsClockEnabled(kCLOCK_Lpspi3) &&
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!bsp::IsClockEnabled(kCLOCK_Lpspi4) && !bsp::IsClockEnabled(kCLOCK_Usdhc1) &&
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!bsp::IsClockEnabled(kCLOCK_Usdhc2)) {
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/* Disable PLL2 */
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clkPLL2setup(CLK_DISABLE);
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/* Switch DCDC to low power config */
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bsp::dcdc::SwitchToLowPowerConfig();
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/* Switch to low power LDO */
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bsp::ldo::SwitchToLowPowerMode();
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/* Switch to low power bandgap */
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bsp::bandgap::SwitchToLowPowerMode();
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}
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}
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bool RT1051DriverPLL2::IsPLL2Enabled() const noexcept
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{
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return not static_cast<bool>(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK);
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}
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} // namespace drivers
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