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8b3ae7b48c
* Fix of the issue that source clock for PWM module was improperly assumed to be derived from AHB_CLK, while in reality it is derived from IPG_CLK, what resulted in module generating signal with 4 times lower frequency than the configured one. * Cleanups.
39 lines
785 B
C++
39 lines
785 B
C++
// Copyright (c) 2017-2021, Mudita Sp. z.o.o. All rights reserved.
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// For licensing, see https://github.com/mudita/MuditaOS/LICENSE.md
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#pragma once
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#include <cstdint>
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namespace bsp
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{
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enum class RetCode
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{
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Success,
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Failure
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};
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/// CPU frequency is dependent on the clock settings.
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/// Only a few thresholds are available in the current configuration
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enum class CpuFrequencyMHz
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{
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Level_0 = 4,
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Level_1 = 12,
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Level_2 = 24,
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Level_3 = 66,
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Level_4 = 132,
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Level_5 = 264,
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Level_6 = 528
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};
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enum class Board
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{
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RT1051,
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Linux,
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None
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};
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[[nodiscard]] std::uint8_t CpuMHZToLevel(CpuFrequencyMHz val);
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[[nodiscard]] const char *c_str(Board board);
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}
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