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74e6a50989
There is a memory shortage in the DTCM region. In order to be able to add new features linker script for the rt1051 needs to be cleanup. A couple of issues has been fixed: * double stack definition blocking 4kB * excessive heap definition blocking 4kB * a part of DTCM had not been used blocking 24kB. Data has been split to user and system part, user data has been moved to the SDRAM, therefore new data will be placed there. To place it inside the MCU an explicit statement has to be used. Added a basic description of memory layout and a couple of comments. Signed-off-by: Marcin Smoczyński <smoczynski.marcin@gmail.com>
193 lines
4.7 KiB
Plaintext
193 lines
4.7 KiB
Plaintext
/*
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* (c) Code Red Technologies Ltd, 2008-2013
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* (c) NXP Semiconductors 2013-2018
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* Generated linker script file for MIMXRT1052xxxxB
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v10.2.0 [Build 759] [2018-05-15] on 2018-07-30 10:43:20
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*
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* Modified by Mudita
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*/
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ENTRY(ResetISR)
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__ocram_noncached_start = ORIGIN(SRAM_OC);
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__ocram_noncached_end = ORIGIN(SRAM_OC) + LENGTH(SRAM_OC);
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__dtcm_ram_start = ORIGIN(SRAM_DTC);
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__dtcm_ram_end = ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC);
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__sdram_cached_start = ORIGIN(BOARD_SDRAM_HEAP);
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__sdram_cached_end = ORIGIN(BOARD_SDRAM_HEAP) + LENGTH(BOARD_SDRAM_HEAP);
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SECTIONS
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{
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/* Image Vector Table and Boot Data for booting from external flash */
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.boot_hdr : ALIGN(4)
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{
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FILL(0x00)
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__boot_hdr_start__ = ABSOLUTE(.) ;
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KEEP(*(.boot_hdr.conf))
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. = 0x400 ;
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KEEP(*(.boot_hdr.ivt))
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. = 0x420 ;
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KEEP(*(.boot_hdr.boot_data))
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. = 0x430 ;
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KEEP(*(.boot_hdr.dcd_data))
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__boot_hdr_end__ = ABSOLUTE(.) ;
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. = 0x2000 ;
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} > BOARD_SDRAM_TEXT
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/* Data sections descriptors for startup initialization */
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.text : ALIGN(4)
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{
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FILL(0x00)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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/* System data */
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LONG(LOADADDR(.sysdata));
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LONG( ADDR(.sysdata));
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LONG( SIZEOF(.sysdata));
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/* User data */
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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__data_section_table_end = .;
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__bss_section_table = .;
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/* System bss */
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LONG( ADDR(.sysbss));
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LONG( SIZEOF(.sysbss));
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/* User bss */
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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} > BOARD_SDRAM_TEXT
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/* Init code */
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.text : ALIGN(4)
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{
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*(.after_vectors*)
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} > BOARD_SDRAM_TEXT
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/* System uninitialized data */
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.sysbss : ALIGN(4)
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{
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*(NonCacheable)
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*(COMMON)
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lib/libmodule-os.a:*(.bss*)
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lib/libmodule-sys.a:*(.bss*)
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lib/libmodule-bsp.a:*(.bss*)
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} > SRAM_DTC
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/* System initialized data */
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.sysdata : ALIGN(4)
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{
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*(NonCacheable.init)
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*(.ramfunc*)
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lib/libmodule-os.a:*(.data*)
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lib/libmodule-sys.a:*(.data*)
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lib/libmodule-bsp.a:*(.data*)
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} > SRAM_DTC AT > BOARD_SDRAM_TEXT
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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/* C++ constructors etc */
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. = ALIGN(4);
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KEEP(*(.init))
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. = ALIGN(4);
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__preinit_array_start = .;
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KEEP (*(.preinit_array))
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__preinit_array_end = .;
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. = ALIGN(4);
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__init_array_end = .;
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KEEP(*(.fini));
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. = ALIGN(4);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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. = ALIGN(4);
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/* End of C++ support */
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} > BOARD_SDRAM_TEXT
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/* Exception handling */
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > BOARD_SDRAM_TEXT
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.ARM.exidx : ALIGN(4)
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{
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > BOARD_SDRAM_TEXT
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/* Main DATA section (SDRAM) */
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.data : ALIGN(4)
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{
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FILL(0xff)
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_data = . ;
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*(vtable)
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*(.data*)
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. = ALIGN(4) ;
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_edata = . ;
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} > BOARD_SDRAM_TEXT
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/* MAIN BSS SECTION */
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.bss : ALIGN(4)
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{
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_bss = .;
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*(.bss*)
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. = ALIGN(4) ;
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_ebss = .;
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PROVIDE(end = .);
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} > BOARD_SDRAM_TEXT
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/* ext SDRAM */
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.sdram (NOLOAD) : ALIGN(4)
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{
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*(.sdram)
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*(.sdram.*)
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} >BOARD_SDRAM_HEAP
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/* DMA buffers */
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.intramnoncacheable (NOLOAD) : ALIGN(4)
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{
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*(.intramnoncacheable)
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*(.intramnoncacheable.*)
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} > SRAM_OC
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/* Place system stack at the very end of DTCM */
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_StackSize = 0x1000;
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.stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0 : ALIGN(4)
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{
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_vStackBase = .;
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. = ALIGN(4);
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_vStackTop = . + _StackSize;
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} > SRAM_DTC
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}
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