From c706d22f743fc1bac8001a195d228c14dcf3bd59 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Wed, 19 Aug 2026 19:16:51 -0700 Subject: [PATCH 01/54] nbio: fix lost lake-up and stale op.l on windows --- core/nbio/impl_windows.odin | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index 162092a80..d9e43f378 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -25,11 +25,6 @@ _Event_Loop :: struct { thread: win.HANDLE, completed: queue.Queue(^Operation), completed_oob: Multi_Producer_Single_Consumer, - state: enum { - Working, - Waking, - Sleeping, - }, } @(private="package") @@ -176,12 +171,8 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { } if actual_timeout > 0 { - sync.atomic_store_explicit(&l.state, .Sleeping, .Release) - - // There could be a race condition where we go sleeping at the same time as things get queued - // and a wakeup isn't done because the state is not .Sleeping yet. - // So after sleeping we first check our queues. - + // Work may have been queued after the drain at the top of this tick, + // so check the queues once more before blocking. for { op := (^Operation)(mpsc_dequeue(&l.queue)) if op == nil { break } @@ -209,8 +200,6 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { } } - sync.atomic_store_explicit(&l.state, .Working, .Relaxed) - if actual_timeout > 0 { // We may have just waited some time, lets update the current time. l.now = time.now() @@ -228,7 +217,7 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { handle_completed(op) } else { op_l := op.l - for !mpsc_enqueue(&op.l.completed_oob, op) { + for !mpsc_enqueue(&op_l.completed_oob, op) { warn("oob queue filled up, QUEUE_SIZE may need increasing") _wake_up(op_l) win.SwitchToThread() @@ -770,10 +759,10 @@ _associate_socket :: proc(socket: Any_Socket, l: ^Event_Loop) -> Association_Err @(private="package") _wake_up :: proc(l: ^Event_Loop) { - _, exchanged := sync.atomic_compare_exchange_strong(&l.state, .Sleeping, .Waking) - if exchanged { - win.QueueUserAPC(proc "system" (Parameter: win.ULONG_PTR) {}, l.thread, 0) - } + // Unconditional: an APC queued before the loop enters its alertable wait stays + // pending and is delivered as soon as that wait begins. Queueing it only once the + // loop is already asleep drops every wake sent while it is still awake. + win.QueueUserAPC(proc "system" (Parameter: win.ULONG_PTR) {}, l.thread, 0) } @(private="package") From 2719a089ec943eafe7ffcaab2204640101f94310 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Thu, 20 Aug 2026 20:43:08 -0700 Subject: [PATCH 02/54] recompute timeouts --- core/nbio/impl_windows.odin | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index d9e43f378..2af88afb9 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -160,15 +160,7 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { if pool.num_outstanding(&l.operation_pool) == 0 { return nil } - actual_timeout := win.INFINITE - if queue.len(l.completed) > 0 || mpsc_count(&l.completed_oob) > 0 { - actual_timeout = 0 - } else if timeout >= 0 { - actual_timeout = win.DWORD(timeout / time.Millisecond) - } - if nt, ok := next_timeout.?; ok { - actual_timeout = min(actual_timeout, win.DWORD(nt / time.Millisecond)) - } + actual_timeout := compute_timeout(l, timeout, next_timeout) if actual_timeout > 0 { // Work may have been queued after the drain at the top of this tick, @@ -184,6 +176,10 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { if op == nil { break } handle_completed(op) } + + // The drains can add timeouts, and `timeout_exec` only puts those in + // `l.timeouts` without posting anything + actual_timeout = compute_timeout(l, timeout, check_timeouts(l)) } for { @@ -237,6 +233,19 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { return nil + compute_timeout :: proc(l: ^Event_Loop, timeout: time.Duration, next_timeout: Maybe(time.Duration)) -> win.DWORD { + actual: win.DWORD = win.INFINITE + if queue.len(l.completed) > 0 || mpsc_count(&l.completed_oob) > 0 { + actual = 0 + } else if timeout >= 0 { + actual = win.DWORD(timeout / time.Millisecond) + } + if nt, ok := next_timeout.?; ok { + actual = min(actual, win.DWORD(nt / time.Millisecond)) + } + return actual + } + check_timeouts :: proc(l: ^Event_Loop) -> (expires: Maybe(time.Duration)) { curr := l.now From ae56bf54564bd88018bc0cf4984dd8194d6a637c Mon Sep 17 00:00:00 2001 From: kalsprite Date: Thu, 20 Aug 2026 23:04:26 -0700 Subject: [PATCH 03/54] nbio(windows): clear the OVERLAPPED when arming a poll; nbio(windows): tear down poll waits before their event; nbio(windows): clear the socket event record on poll completion --- core/nbio/impl_windows.odin | 39 ++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index 2af88afb9..a8c99e05b 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -676,7 +676,7 @@ _remove :: proc(target: ^Operation) { switch target.type { case .Poll: - win.UnregisterWaitEx(target.poll._impl.wait_handle, nil) + win.UnregisterWaitEx(target.poll._impl.wait_handle, win.INVALID_HANDLE_VALUE) target.poll._impl.wait_handle = nil ok := win.PostQueuedCompletionStatus( @@ -1500,9 +1500,14 @@ sendfile_callback :: proc(op: ^Operation) -> Op_Result { return .Done } +// Bit indices into `WSANETWORKEVENTS.iErrorCode`, corresponding to the `FD_*` masks. +FD_READ_BIT :: 0 +FD_WRITE_BIT :: 1 + @(require_results) poll_exec :: proc(op: ^Operation) -> Op_Result { assert(op.type == .Poll) + op._impl.over = {} // Operations are recycled, clear stale state from a previous use. events: i32 = win.FD_CLOSE switch op.poll.event { @@ -1565,12 +1570,40 @@ poll_exec :: proc(op: ^Operation) -> Op_Result { poll_callback :: proc(op: ^Operation) { assert(op.type == .Poll) + // Clear the socket's internal network event record, and find out what actually + // fired. Without this the record stays set after an event is reported, so the next + // `WSAEventSelect` on that socket signals its event object immediately from the + // stale record. That completes a poll for a readiness that never happened, and the + // send/recv the caller then makes fails with WOULDBLOCK. if op._impl.over.hEvent != nil { - win.WSACloseEvent(op._impl.over.hEvent) + nev: win.WSANETWORKEVENTS + sk := win.SOCKET(net.any_socket_to_socket(op.poll.socket)) + if win.WSAEnumNetworkEvents(sk, op._impl.over.hEvent, &nev) == 0 { + bit: uint + switch op.poll.event { + case .Receive: bit = FD_READ_BIT + case .Send: bit = FD_WRITE_BIT + } + + // Only downgrade a result that is still `Ready`; `wait_callback` may have + // already set `.Timeout`. + if op.poll.result == nil && nev.lNetworkEvents & (i32(1) << bit) != 0 && nev.iErrorCode[bit] != 0 { + op.poll.result = .Error + } + } } + // Tear down in the reverse order of `poll_exec`: stop `wait_callback` from running + // before the event it waits on goes away. `INVALID_HANDLE_VALUE` waits for an + // in-flight callback to return, so it can't touch `op` after it is recycled. if op.poll._impl.wait_handle != nil { - win.UnregisterWaitEx(op.poll._impl.wait_handle, nil) + win.UnregisterWaitEx(op.poll._impl.wait_handle, win.INVALID_HANDLE_VALUE) + op.poll._impl.wait_handle = nil + } + + if op._impl.over.hEvent != nil { + win.WSACloseEvent(op._impl.over.hEvent) + op._impl.over.hEvent = nil } if op.poll.result != nil { From bcf2dcd2f0afeac70bb28ba88f0299c1ae0b11f9 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Thu, 20 Aug 2026 23:39:21 -0700 Subject: [PATCH 04/54] nbio(windows): don't complete synchronously-failed overlapped ops twice --- core/nbio/impl_windows.odin | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index a8c99e05b..de16a5a69 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -923,6 +923,9 @@ accept_exec :: proc(op: ^Operation) -> Op_Result { return .Pending } else if op._impl.over.Internal == nil { op.accept.err = net._accept_error() + } else { + link_timeout(op, op.accept.expires) + return .Pending } } @@ -1024,6 +1027,9 @@ dial_exec :: proc(op: ^Operation) -> (result: Op_Result) { return .Pending } else if op._impl.over.Internal == nil { op.dial.err = net._dial_error() + } else { + link_timeout(op, op.dial.expires) + return .Pending } } @@ -1083,6 +1089,13 @@ read_exec :: proc(op: ^Operation) -> Op_Result { return .Pending } op.read.err = FS_Error(err) + } else { + // The read completed synchronously with a failure status. `FILE_SKIP_COMPLETION_PORT_ON_SUCCESS` + // only suppresses the completion packet on success, so one is still queued for + // this. Returning `.Done` here would complete the operation a second time, on an + // Operation that has already been recycled into the pool. + link_timeout(op, op.read.expires) + return .Pending } } @@ -1157,6 +1170,9 @@ write_exec :: proc(op: ^Operation) -> Op_Result { return .Pending } op.write.err = FS_Error(err) + } else { + link_timeout(op, op.write.expires) + return .Pending } } @@ -1250,6 +1266,9 @@ recv_exec :: proc(op: ^Operation) -> Op_Result { case TCP_Socket: op.recv.err = net._tcp_recv_error() case UDP_Socket: op.recv.err = net._udp_recv_error() } + } else { + link_timeout(op, op.recv.expires) + return .Pending } } @@ -1368,6 +1387,9 @@ send_exec :: proc(op: ^Operation) -> Op_Result { case TCP_Socket: op.send.err = net._tcp_send_error() case UDP_Socket: op.send.err = net._udp_send_error() } + } else { + link_timeout(op, op.send.expires) + return .Pending } } @@ -1457,6 +1479,9 @@ sendfile_exec :: proc(op: ^Operation) -> Op_Result { return .Pending } else if op._impl.over.Internal == nil { op.sendfile.err = net._tcp_send_error() + } else { + link_timeout(op, op.sendfile.expires) + return .Pending } } From 6e690afaf1d455cf29c7997839f2a39e9d226a42 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Fri, 21 Aug 2026 00:09:43 -0700 Subject: [PATCH 05/54] revert wake change --- core/nbio/impl_windows.odin | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index de16a5a69..e1e0f2ebc 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -25,6 +25,11 @@ _Event_Loop :: struct { thread: win.HANDLE, completed: queue.Queue(^Operation), completed_oob: Multi_Producer_Single_Consumer, + state: enum { + Working, + Waking, + Sleeping, + }, } @(private="package") @@ -163,8 +168,11 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { actual_timeout := compute_timeout(l, timeout, next_timeout) if actual_timeout > 0 { - // Work may have been queued after the drain at the top of this tick, - // so check the queues once more before blocking. + sync.atomic_store_explicit(&l.state, .Sleeping, .Release) + + // There could be a race condition where we go sleeping at the same time as things get queued + // and a wakeup isn't done because the state is not .Sleeping yet. + // So after sleeping we first check our queues. for { op := (^Operation)(mpsc_dequeue(&l.queue)) if op == nil { break } @@ -196,6 +204,8 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { } } + sync.atomic_store_explicit(&l.state, .Working, .Relaxed) + if actual_timeout > 0 { // We may have just waited some time, lets update the current time. l.now = time.now() @@ -768,10 +778,10 @@ _associate_socket :: proc(socket: Any_Socket, l: ^Event_Loop) -> Association_Err @(private="package") _wake_up :: proc(l: ^Event_Loop) { - // Unconditional: an APC queued before the loop enters its alertable wait stays - // pending and is delivered as soon as that wait begins. Queueing it only once the - // loop is already asleep drops every wake sent while it is still awake. - win.QueueUserAPC(proc "system" (Parameter: win.ULONG_PTR) {}, l.thread, 0) + _, exchanged := sync.atomic_compare_exchange_strong(&l.state, .Sleeping, .Waking) + if exchanged { + win.QueueUserAPC(proc "system" (Parameter: win.ULONG_PTR) {}, l.thread, 0) + } } @(private="package") From d2da33235d3a63b418097bc42812ada9696f7672 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Fri, 21 Aug 2026 09:18:57 -0700 Subject: [PATCH 06/54] nbio(windows): handle queued work in the tick that was woken for it; nbio(tests): let wake_up tolerate a tick that returns without progress --- core/nbio/impl_windows.odin | 14 ++++++++++++++ tests/core/nbio/nbio.odin | 7 +++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index e1e0f2ebc..7357f7c18 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -241,6 +241,20 @@ __tick :: proc(l: ^Event_Loop, timeout: time.Duration) -> (err: General_Error) { actual_timeout = 0 } + // A wake, or another loop routing a completion to us, can leave work queued. + // Handle it here instead of waiting for the caller to tick again. + for { + op := (^Operation)(mpsc_dequeue(&l.queue)) + if op == nil { break } + _exec(op) + } + + for { + op := (^Operation)(mpsc_dequeue(&l.completed_oob)) + if op == nil { break } + handle_completed(op) + } + return nil compute_timeout :: proc(l: ^Event_Loop, timeout: time.Duration, next_timeout: Maybe(time.Duration)) -> win.DWORD { diff --git a/tests/core/nbio/nbio.odin b/tests/core/nbio/nbio.odin index 6121d1ac7..5d43fd814 100644 --- a/tests/core/nbio/nbio.odin +++ b/tests/core/nbio/nbio.odin @@ -244,8 +244,11 @@ wake_up :: proc(t: ^testing.T) { }, context) defer thread.destroy(thr) - // Should block forever until the thread calling wake_up will make it return. - ev(t, nbio.tick(), nil) + // A tick can return without progress; loop until the wake is observed. + // A lost wake would block here forever and trip the fail timeout. + for !hit { + ev(t, nbio.tick(), nil) + } e(t, hit) nbio.remove(accept) From 1b4e14fbc549e532fe5e2fc614ab66502e849c93 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Fri, 21 Aug 2026 20:43:33 -0700 Subject: [PATCH 07/54] restore fail timeout --- tests/core/nbio/net.odin | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/core/nbio/net.odin b/tests/core/nbio/net.odin index 77e44f73b..f0b8226c6 100644 --- a/tests/core/nbio/net.odin +++ b/tests/core/nbio/net.odin @@ -245,7 +245,7 @@ And it tests big send/recv buffers being handled properly. @(test) poll :: proc(t: ^testing.T) { if event_loop_guard(t) { -// testing.set_fail_timeout(t, time.Minute) + testing.set_fail_timeout(t, time.Minute) can_recv: bool From 7bb55ba45b4c1d463e1f096fcde35e15052c5fa9 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Fri, 21 Aug 2026 21:31:49 -0700 Subject: [PATCH 08/54] nbio(windows): poll sockets through AFD --- core/nbio/impl_windows.odin | 224 +++++++++++++++++++++--------------- core/nbio/ops.odin | 12 ++ core/sys/windows/ntdll.odin | 13 +++ tests/core/nbio/remove.odin | 17 ++- 4 files changed, 167 insertions(+), 99 deletions(-) diff --git a/core/nbio/impl_windows.odin b/core/nbio/impl_windows.odin index 7357f7c18..4d202620e 100644 --- a/core/nbio/impl_windows.odin +++ b/core/nbio/impl_windows.odin @@ -19,6 +19,38 @@ import win "core:sys/windows" @(private="package") _FULLY_SUPPORTED :: true +// Poll is driven by AFD, the socket driver underneath winsock. +// `WSAEventSelect` is edge triggered (`FD_WRITE` is only recorded again after a +// send fails with WOULDBLOCK) and neither `select` nor `WSAPoll` reports send +// buffer space, so neither can give the level triggered readiness `poll` promises. +// AFD also completes on the IOCP, which makes a poll an ordinary overlapped operation. +IOCTL_AFD_POLL :: 0x00012024 +SIO_BASE_HANDLE :: win.DWORD(0x48000022) + +AFD_POLL_RECEIVE :: 0x0001 +AFD_POLL_RECEIVE_EXPEDITED :: 0x0002 +AFD_POLL_SEND :: 0x0004 +AFD_POLL_DISCONNECT :: 0x0008 +AFD_POLL_ABORT :: 0x0010 +AFD_POLL_LOCAL_CLOSE :: 0x0020 +AFD_POLL_ACCEPT :: 0x0080 +AFD_POLL_CONNECT_FAIL :: 0x0100 + +AFD_Poll_Handle_Info :: struct { + handle: win.HANDLE, + events: win.ULONG, + status: win.NTSTATUS, +} + +AFD_Poll_Info :: struct { + timeout: i64, + number_of_handles: win.ULONG, + exclusive: win.ULONG, + handles: [1]AFD_Poll_Handle_Info, +} + +afd_device_name := [?]u16{'\\','D','e','v','i','c','e','\\','A','f','d','\\','E','n','d','p','o','i','n','t'} + @(private="package") _Event_Loop :: struct { timeouts: avl.Tree(^Operation), @@ -88,7 +120,7 @@ _Timeout :: struct { @(private="package") _Poll :: struct { - wait_handle: win.HANDLE, + info: AFD_Poll_Info, } @(private="package") @@ -699,19 +731,6 @@ _remove :: proc(target: ^Operation) { target._impl.timeout = (^Operation)(REMOVED) switch target.type { - case .Poll: - win.UnregisterWaitEx(target.poll._impl.wait_handle, win.INVALID_HANDLE_VALUE) - target.poll._impl.wait_handle = nil - - ok := win.PostQueuedCompletionStatus( - g.iocp, - 0, - 0, - &target._impl.over, - ) - ensure(ok == true, "unexpected PostQueuedCompletionStatus error") - return - case .Timeout: if avl.remove_value(&target.l.timeouts, target) { debug("removed timeout directly") @@ -727,6 +746,17 @@ _remove :: proc(target: ^Operation) { // Synchronous ops, picked up in handler. return + case .Poll: + // The poll may have completed already, with its completion queued but not yet + // handled, `NOT_FOUND` is expected rather than exceptional. + if !win.CancelIoEx(g.afd, &target._impl.over) { + #partial switch win.System_Error(win.GetLastError()) { + case .NOT_FOUND: + // nop + case: assert(false, "unexpected CancelIoEx error") + } + } + case .Accept, .Dial, .Read, .Recv, .Send, .Write, .Send_File: if is_pending(target._impl.over) { handle := operation_handle(target) @@ -824,6 +854,7 @@ g: struct{ mu: sync.Mutex, refs: int, iocp: win.HANDLE, + afd: win.HANDLE, err: General_Error, } @@ -839,6 +870,36 @@ g_ref :: proc() -> General_Error { if g.iocp == nil { g.err = General_Error(win.GetLastError()) } + + if g.err != nil { return g.err } + + // A handle on the socket driver, used to poll sockets for readiness. + iosb: win.IO_STATUS_BLOCK + status := win.NtCreateFile( + &g.afd, + win.SYNCHRONIZE, + &{ + Length = size_of(win.OBJECT_ATTRIBUTES), + ObjectName = &{ + Length = u16(len(afd_device_name)*2), + MaximumLength = u16(len(afd_device_name)*2), + Buffer = raw_data(afd_device_name[:]), + }, + }, + &iosb, + nil, + 0, + win.FILE_SHARE_READ|win.FILE_SHARE_WRITE, + win.FILE_OPEN, + 0, + nil, + 0, + ) + if syserr := win.System_Error(win.RtlNtStatusToDosError(status)); syserr != .SUCCESS { + g.err = General_Error(syserr) + } else if win.CreateIoCompletionPort(g.afd, g.iocp, 0, 0) != g.iocp { + g.err = General_Error(win.GetLastError()) + } } sync.atomic_add(&g.refs, 1) @@ -850,6 +911,7 @@ g_unref :: proc() { sync.guard(&g.mu) if sync.atomic_sub(&g.refs, 1) == 1 { + if g.afd != nil { win.CloseHandle(g.afd) } win.CloseHandle(g.iocp) g.err = nil } @@ -872,7 +934,7 @@ operation_handle :: proc(op: ^Operation) -> win.HANDLE { case .Recv: return win.HANDLE(uintptr(net.any_socket_to_socket(op.recv.socket))) case .Send: return win.HANDLE(uintptr(net.any_socket_to_socket(op.send.socket))) case .Send_File: return win.HANDLE(uintptr(net.any_socket_to_socket(op.sendfile.socket))) - case .Poll: return win.HANDLE(uintptr(net.any_socket_to_socket(op.poll.socket))) + case .Poll: return g.afd case .Stat: return win.HANDLE(uintptr(op.stat.handle)) case .Timeout, .Open, ._Splice, ._Link_Timeout, ._Remove, .None: @@ -1549,120 +1611,94 @@ sendfile_callback :: proc(op: ^Operation) -> Op_Result { return .Done } -// Bit indices into `WSANETWORKEVENTS.iErrorCode`, corresponding to the `FD_*` masks. -FD_READ_BIT :: 0 -FD_WRITE_BIT :: 1 - @(require_results) poll_exec :: proc(op: ^Operation) -> Op_Result { assert(op.type == .Poll) op._impl.over = {} // Operations are recycled, clear stale state from a previous use. - events: i32 = win.FD_CLOSE + events: win.ULONG = AFD_POLL_ABORT|AFD_POLL_DISCONNECT|AFD_POLL_LOCAL_CLOSE|AFD_POLL_CONNECT_FAIL switch op.poll.event { - case .Send: events |= win.FD_WRITE|win.FD_CONNECT - case .Receive: events |= win.FD_READ|win.FD_ACCEPT + case .Receive: events |= AFD_POLL_RECEIVE|AFD_POLL_RECEIVE_EXPEDITED|AFD_POLL_ACCEPT + case .Send: events |= AFD_POLL_SEND case: op.poll.result = .Invalid_Argument return .Done } - op._impl.over.hEvent = win.WSACreateEvent() - if win.WSAEventSelect( + // AFD needs the socket underneath any layered service providers. + base: win.SOCKET + bytes: win.DWORD + if win.WSAIoctl( win.SOCKET(net.any_socket_to_socket(op.poll.socket)), - op._impl.over.hEvent, - events, + SIO_BASE_HANDLE, + nil, 0, + &base, size_of(base), + &bytes, nil, nil, ) != 0 { - #partial switch win.System_Error(win.GetLastError()) { + #partial switch win.System_Error(win.WSAGetLastError()) { case .WSAEINVAL, .WSAENOTSOCK: op.poll.result = .Invalid_Argument case: op.poll.result = .Error } return .Done } - timeout := win.INFINITE + // A negative timeout is relative, in 100ns units. + timeout := max(i64) if op.poll.expires != {} { diff := max(0, time.diff(op.l.now, op.poll.expires)) - timeout = win.DWORD(diff / time.Millisecond) + timeout = -i64(diff / 100) } - ok := win.RegisterWaitForSingleObject( - &op.poll._impl.wait_handle, - op._impl.over.hEvent, - wait_callback, - op, - timeout, - win.WT_EXECUTEINWAITTHREAD|win.WT_EXECUTEONLYONCE, + op.poll._impl.info = { + timeout = timeout, + number_of_handles = 1, + handles = {{handle = win.HANDLE(uintptr(base)), events = events}}, + } + + // The OVERLAPPED doubles as the IO_STATUS_BLOCK, their first two fields line up. + status := win.NtDeviceIoControlFile( + g.afd, + nil, + nil, + &op._impl.over, + win.PIO_STATUS_BLOCK(rawptr(&op._impl.over)), + IOCTL_AFD_POLL, + &op.poll._impl.info, + size_of(AFD_Poll_Info), + &op.poll._impl.info, + size_of(AFD_Poll_Info), ) - ensure(ok == true, "unexpected RegisterWaitForSingleObject error") - return .Pending - - wait_callback :: proc "system" (lpParameter: win.PVOID, TimerOrWaitFired: win.BOOLEAN) { - op := (^Operation)(lpParameter) - assert_contextless(op.type == .Poll) - - if TimerOrWaitFired { - op.poll.result = .Timeout - } - - ok := win.PostQueuedCompletionStatus( - g.iocp, - 0, - 0, - &op._impl.over, - ) - ensure_contextless(ok == true, "unexpected PostQueuedCompletionStatus error") + // The AFD handle is not set to skip completion on success, so a completion is + // queued even when this finishes synchronously. + #partial switch win.System_Error(win.RtlNtStatusToDosError(status)) { + case .SUCCESS, .IO_PENDING: + return .Pending + case: + op.poll.result = .Error + return .Done } } poll_callback :: proc(op: ^Operation) { assert(op.type == .Poll) - // Clear the socket's internal network event record, and find out what actually - // fired. Without this the record stays set after an event is reported, so the next - // `WSAEventSelect` on that socket signals its event object immediately from the - // stale record. That completes a poll for a readiness that never happened, and the - // send/recv the caller then makes fails with WOULDBLOCK. - if op._impl.over.hEvent != nil { - nev: win.WSANETWORKEVENTS - sk := win.SOCKET(net.any_socket_to_socket(op.poll.socket)) - if win.WSAEnumNetworkEvents(sk, op._impl.over.hEvent, &nev) == 0 { - bit: uint - switch op.poll.event { - case .Receive: bit = FD_READ_BIT - case .Send: bit = FD_WRITE_BIT - } - - // Only downgrade a result that is still `Ready`; `wait_callback` may have - // already set `.Timeout`. - if op.poll.result == nil && nev.lNetworkEvents & (i32(1) << bit) != 0 && nev.iErrorCode[bit] != 0 { - op.poll.result = .Error - } - } - } - - // Tear down in the reverse order of `poll_exec`: stop `wait_callback` from running - // before the event it waits on goes away. `INVALID_HANDLE_VALUE` waits for an - // in-flight callback to return, so it can't touch `op` after it is recycled. - if op.poll._impl.wait_handle != nil { - win.UnregisterWaitEx(op.poll._impl.wait_handle, win.INVALID_HANDLE_VALUE) - op.poll._impl.wait_handle = nil - } - - if op._impl.over.hEvent != nil { - win.WSACloseEvent(op._impl.over.hEvent) - op._impl.over.hEvent = nil - } - if op.poll.result != nil { return } - _, err := get_result(op._impl.over) - #partial switch err { - case .SUCCESS: - case: + // AFD reports a timeout by coming back with no handles. + if op.poll._impl.info.number_of_handles == 0 { + op.poll.result = .Timeout + return + } + + if _, err := get_result(op._impl.over); err != .SUCCESS { + op.poll.result = .Error + return + } + + if op.poll._impl.info.handles[0].events & (AFD_POLL_ABORT|AFD_POLL_CONNECT_FAIL) != 0 { op.poll.result = .Error } } diff --git a/core/nbio/ops.odin b/core/nbio/ops.odin index 382dca747..6af266e72 100644 --- a/core/nbio/ops.odin +++ b/core/nbio/ops.odin @@ -1626,6 +1626,9 @@ Poll a socket for readiness. NOTE: this is provided to help with "legacy" APIs that require polling behavior. If you can avoid it and use the other procs in this package, do so. +NOTE: on Windows only one poll per socket is delivered, a second poll on the same +socket does not complete. + Any user data can be set on the returned operation's `user_data` field. Polymorphic variants for type safe user data are available under `poll_poly`, `poll_poly2`, and `poll_poly3`. @@ -1656,6 +1659,9 @@ Poll a socket for readiness. NOTE: this is provided to help with "legacy" APIs that require polling behavior. If you can avoid it and use the other procs in this package, do so. +NOTE: on Windows only one poll per socket is delivered, a second poll on the same +socket does not complete. + This procedure uses polymorphism for type safe user data up to a certain size. Inputs: @@ -1690,6 +1696,9 @@ Poll a socket for readiness. NOTE: this is provided to help with "legacy" APIs that require polling behavior. If you can avoid it and use the other procs in this package, do so. +NOTE: on Windows only one poll per socket is delivered, a second poll on the same +socket does not complete. + This procedure uses polymorphism for type safe user data up to a certain size. Inputs: @@ -1725,6 +1734,9 @@ Poll a socket for readiness. NOTE: this is provided to help with "legacy" APIs that require polling behavior. If you can avoid it and use the other procs in this package, do so. +NOTE: on Windows only one poll per socket is delivered, a second poll on the same +socket does not complete. + This procedure uses polymorphism for type safe user data up to a certain size. Inputs: diff --git a/core/sys/windows/ntdll.odin b/core/sys/windows/ntdll.odin index 41deaa1c4..a78228642 100644 --- a/core/sys/windows/ntdll.odin +++ b/core/sys/windows/ntdll.odin @@ -7,6 +7,19 @@ foreign import ntdll_lib "system:ntdll.lib" foreign ntdll_lib { RtlGetVersion :: proc(lpVersionInformation: ^OSVERSIONINFOEXW) -> NTSTATUS --- + NtDeviceIoControlFile :: proc( + FileHandle: HANDLE, + Event: HANDLE, + ApcRoutine: PIO_APC_ROUTINE, + ApcContext: rawptr, + IoStatusBlock: PIO_STATUS_BLOCK, + IoControlCode: ULONG, + InputBuffer: rawptr, + InputBufferLength: ULONG, + OutputBuffer: rawptr, + OutputBufferLength: ULONG, + ) -> NTSTATUS --- + NtQueryInformationProcess :: proc( ProcessHandle: HANDLE, diff --git a/tests/core/nbio/remove.odin b/tests/core/nbio/remove.odin index 063c2cf58..37d32c5e1 100644 --- a/tests/core/nbio/remove.odin +++ b/tests/core/nbio/remove.odin @@ -212,13 +212,18 @@ remove_multiple_poll :: proc(t: ^testing.T) { if event_loop_guard(t) { testing.set_fail_timeout(t, time.Minute) - sock, ep := open_next_available_local_port(t) - defer nbio.close(sock) + // Two sockets rather than two polls on one socket: only one poll per socket is + // delivered on Windows, and what this tests is removal, not that. + removed_sock, removed_ep := open_next_available_local_port(t) + defer nbio.close(removed_sock) + + kept_sock, kept_ep := open_next_available_local_port(t) + defer nbio.close(kept_sock) hit: bool - first := nbio.poll(sock, .Receive, on_poll) - nbio.poll_poly2(sock, .Receive, t, &hit, on_poll2) + first := nbio.poll(removed_sock, .Receive, on_poll) + nbio.poll_poly2(kept_sock, .Receive, t, &hit, on_poll2) on_poll :: proc(op: ^nbio.Operation) { log.error("shouldn't be called") @@ -235,7 +240,9 @@ remove_multiple_poll :: proc(t: ^testing.T) { ev(t, nbio.tick(0), nil) - nbio.dial_poly(ep, t, on_dial) + // Make both readable, the removed poll must still not fire. + nbio.dial_poly(removed_ep, t, on_dial) + nbio.dial_poly(kept_ep, t, on_dial) on_dial :: proc(op: ^nbio.Operation, t: ^testing.T) { ev(t, op.dial.err, nil) From d29b2cadbd1bb3709f789f02e8ddfbc9078b98f0 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Fri, 21 Aug 2026 21:58:40 -0700 Subject: [PATCH 09/54] nbio(tests): fill the socket until sending blocks --- tests/core/nbio/net.odin | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tests/core/nbio/net.odin b/tests/core/nbio/net.odin index f0b8226c6..544fb6f58 100644 --- a/tests/core/nbio/net.odin +++ b/tests/core/nbio/net.odin @@ -302,13 +302,25 @@ poll :: proc(t: ^testing.T) { on_poll1 :: proc(op: ^nbio.Operation, t: ^testing.T, can_recv: ^bool) { ev(t, op.poll.result, nil) - // Send 4 GB of data, which in my experience causes a Would_Block error because we filled up the internal buffer. + // Fill the socket until sending actually blocks. How much that takes depends + // on the machine's socket buffers, so keep sending rather than assuming a + // fixed amount does it. Nothing is reading yet, so this terminates. buf, mem_err := make([]byte, mem.Gigabyte*4, context.temp_allocator) ev(t, mem_err, nil) // Use `core:net` as example external code that doesn't care about the event loop. net.set_blocking(op.poll.socket, false) - n, send_err := net.send(op.poll.socket, buf) + + n: int + send_err: net.Network_Error + for _ in 0..<16 { + sent: int + sent, send_err = net.send(op.poll.socket, buf) + n += sent + if send_err != nil { + break + } + } ev(t, send_err, net.TCP_Send_Error.Would_Block) log.debugf("blocking after %M", n) From fe52f23b502c7ca7132dd16a13674685e5865679 Mon Sep 17 00:00:00 2001 From: kalsprite Date: Fri, 21 Aug 2026 15:25:18 -0700 Subject: [PATCH 10/54] tests/core/nbio/remove.odin --- tests/core/nbio/remove.odin | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/tests/core/nbio/remove.odin b/tests/core/nbio/remove.odin index 37d32c5e1..fe7884c28 100644 --- a/tests/core/nbio/remove.odin +++ b/tests/core/nbio/remove.odin @@ -58,7 +58,12 @@ immediate_remove_of_sendfile :: proc(t: ^testing.T) { } on_recv :: proc(op: ^nbio.Operation, t: ^testing.T) { - ev(t, op.recv.err, nil) + // The server cancelled a sendfile that had already put bytes on the wire and + // then closed, which ends the connection with a reset rather than gracefully + // often enough that both have to be accepted here. + if op.recv.err != nil { + ev(t, op.recv.err, net.TCP_Recv_Error.Connection_Closed) + } nbio.close(op.recv.socket.(net.TCP_Socket)) } @@ -126,7 +131,12 @@ immediate_remove_of_sendfile_without_stat :: proc(t: ^testing.T) { } on_recv :: proc(op: ^nbio.Operation, t: ^testing.T) { - ev(t, op.recv.err, nil) + // The server cancelled a sendfile that had already put bytes on the wire and + // then closed, which ends the connection with a reset rather than gracefully + // often enough that both have to be accepted here. + if op.recv.err != nil { + ev(t, op.recv.err, net.TCP_Recv_Error.Connection_Closed) + } nbio.close(op.recv.socket.(net.TCP_Socket)) } From 52e7244cbbfb50d90ea2f38cd7bbaafdacf26584 Mon Sep 17 00:00:00 2001 From: Mustafa Furkan Bulut Date: Sun, 23 Aug 2026 23:00:58 +0300 Subject: [PATCH 11/54] add windows to the list --- src/build_settings.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/build_settings.cpp b/src/build_settings.cpp index 7932bd635..453934949 100644 --- a/src/build_settings.cpp +++ b/src/build_settings.cpp @@ -2630,12 +2630,13 @@ gb_internal bool init_build_paths(String init_filename) { if (build_context.no_crt && !build_context.no_thread_local) { switch (build_context.metrics.os) { + case TargetOs_windows: case TargetOs_linux: case TargetOs_darwin: case TargetOs_freebsd: case TargetOs_openbsd: case TargetOs_netbsd: - gb_printf_err("-no-crt on Unix systems requires the -no-thread-local flag to also be present, because the TLS is inaccessible without CRT\n"); + gb_printf_err("-no-crt requires the -no-thread-local flag to also be present, because the TLS is inaccessible without CRT\n"); no_crt_checks_failed = true; } } From 2f2ab370e0b51393724a807c37b71adb9a46c53d Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 10:37:59 +0100 Subject: [PATCH 12/54] Fix the actual check for reading from a register that has not be written to yet --- src/check_asm.cpp | 101 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 78 insertions(+), 23 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 3f7bfd9c9..4e626f289 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1487,53 +1487,108 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } u16 pinned_mask = 0; - u16 output_only_pin_mask = 0; for (auto const &ed : tmpl_entity->AsmTemplate.decls) { if (ed.pin.len != 0) { - u16 b = asm_ctx->clobber_bit_for_reg_name(ed.pin); - pinned_mask |= b; - if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) { - output_only_pin_mask |= b; - } + pinned_mask |= asm_ctx->clobber_bit_for_reg_name(ed.pin); } } if (asm_acc->straight_line) { - u16 wants = cast(u16)clobber.implicit_rd & asm_ctx->CLOBBER_REGS_NAMED; - u16 undefined = wants & ~asm_acc->defined_regs & ~pinned_mask; + u16 wants = cast(u16)clobber.implicit_rd & asm_ctx->CLOBBER_REGS_NAMED; + u16 undefined = wants & ~asm_acc->defined_regs; + for (u16 bit = 1; bit != 0; bit <<= 1) { - if ((undefined & bit) == 0) { - continue; - } - char const *rname = asm_ctx->clobber_reg_bit_name(bit); - error(instr->name, - "'%.*s' implicitly reads %%%s, but nothing in this template produces " - "a value for it; pin an input parameter to %%%s, or write %%%s before " - "this instruction", - LIT(name), rname, rname, rname); + if ((undefined & bit) == 0) { + continue; + } + char const *rname = asm_ctx->clobber_reg_bit_name(bit); + + String owner = {}; + char const *role = nullptr; + for (auto const &ed : tmpl_entity->AsmTemplate.decls) { + if (ed.pin.len == 0 || ed.entity == nullptr) { + continue; + } + if (asm_ctx->clobber_bit_for_reg_name(ed.pin) != bit) { + continue; + } + if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) { + owner = ed.entity->token.string; + role = "output"; + break; + } + if (ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0) { + owner = ed.entity->token.string; + role = "scratch"; + break; + } + } + + if (role != nullptr) { + error(instr->name, + "'%.*s' implicitly reads %%%s, which is bound to the %s parameter '%.*s', " + "but nothing has written %%%s yet; write to it (e.g. into '%.*s') before this instruction", + LIT(name), rname, role, LIT(owner), rname, LIT(owner)); + } else { + error(instr->name, + "'%.*s' implicitly reads %%%s, but nothing in this template produces " + "a value for it; pin an input parameter to %%%s, or write %%%s before " + "this instruction", + LIT(name), rname, rname, rname); + } } } u16 produced = cast(u16)clobber.implicit_wr & asm_ctx->CLOBBER_REGS_NAMED; u16 explicit_writes = 0; - // Explicit destination operands that name a concrete register also produce it - // (e.g. `mov eax, $leaf` before CPUID). Only literal %reg operands pin a known - // physical register; parameter operands are register-allocated elsewhere, so they - // don't tell us which physical register was written. u16 written_ops = cast(u16)clobber.written; + u16 pinned_param_writes = 0; for_array(i, operands) { int tslot = user_operand_target_index(cast(int)i); if (tslot < 0 || tslot >= 4 || (written_ops & (1u << tslot)) == 0) { continue; } - Ast *e = operands[i].expr; + auto const &op = operands[i]; + + Ast *e = op.expr; if (e && e->kind == Ast_AsmRegister) { u16 b = asm_ctx->clobber_bit_for_reg_name(e->AsmRegister.name.string); produced |= b; explicit_writes |= b; + } else { + // NOTE(bill): A write through a pinned parameter (or a width-view of one) + // defines that parameter's physical register for the read-before-write check only + auto written_pinned_reg_bit = [&](Operand const &op) -> u16 { + Entity *pe = entity_of_node(op.expr); + if (pe == nullptr || pe->kind != Entity_Variable) { + return 0; + } + auto const &decls = tmpl_entity->AsmTemplate.decls; + for_array(di, decls) { + auto const &ed = decls[di]; + if (ed.entity != pe) { + continue; + } + if (ed.pin.len != 0) { + return asm_ctx->clobber_bit_for_reg_name(ed.pin); + } + // NOTE(bill): A width-view carries no pin of its own and thus it aliases its source's register. + if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) { + String src_pin = decls[ed.view_of].pin; + if (src_pin.len != 0) { + return asm_ctx->clobber_bit_for_reg_name(src_pin); + } + } + return 0; + } + return 0; + }; + + pinned_param_writes |= written_pinned_reg_bit(operands[i]); } } + if (is_pseudo) { // Synthesized register sources (e.g. ra in `jal off` -> `jal ra, off`) also // write a physical register; record them so ra is treated as produced/clobbered. @@ -1550,7 +1605,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm produced |= synth; explicit_writes |= synth; } - asm_acc->defined_regs |= produced; + asm_acc->defined_regs |= produced | pinned_param_writes; // Registers this form clobbers implicitly (RDTSC->RAX:RDX, etc.), for the // redundant-#clobber hint. Union across the template; pinned regs excluded From 74ac336ef1905d487aee85536fb21a173afe2127 Mon Sep 17 00:00:00 2001 From: Mihail Moskov <28909106+corleypc@users.noreply.github.com> Date: Mon, 24 Aug 2026 12:53:05 +0300 Subject: [PATCH 13/54] fixes -o:size --- src/build_settings.cpp | 9 +++++++++ src/llvm_backend.cpp | 1 + src/llvm_backend_general.cpp | 4 ++++ src/llvm_backend_proc.cpp | 7 +++++++ 4 files changed, 21 insertions(+) diff --git a/src/build_settings.cpp b/src/build_settings.cpp index 453934949..714b8af8f 100644 --- a/src/build_settings.cpp +++ b/src/build_settings.cpp @@ -464,6 +464,15 @@ enum IntegerDivisionByZeroKind : u8 { IntegerDivisionByZero_AllBits, }; +// values of BuildContext.optimization_level; +// matches Odin_Optimization_Mode in checker.cpp +enum OptimizationLevel : i32 { + OptimizationLevel_None = -1, + OptimizationLevel_Minimal = 0, + OptimizationLevel_Size = 1, + OptimizationLevel_Speed = 2, + OptimizationLevel_Aggressive = 3, +}; // This stores the information for the specify architecture of this build struct BuildContext { diff --git a/src/llvm_backend.cpp b/src/llvm_backend.cpp index 07f118f20..e770ed90d 100644 --- a/src/llvm_backend.cpp +++ b/src/llvm_backend.cpp @@ -2438,6 +2438,7 @@ gb_internal WORKER_TASK_PROC(lb_llvm_function_pass_per_module) { lbFunctionPassManagerKind pass_manager_kind = lbFunctionPassManager_default; if (p->flags & lbProcedureFlag_WithoutMemcpyPass) { pass_manager_kind = lbFunctionPassManager_default_without_memcpy; + lb_remove_attribute_from_proc(p->module, p->value, "optsize"); // incompatible with optnone lb_add_attribute_to_proc(p->module, p->value, "optnone"); lb_add_attribute_to_proc(p->module, p->value, "noinline"); } else { diff --git a/src/llvm_backend_general.cpp b/src/llvm_backend_general.cpp index 5c77e58df..17b41cfad 100644 --- a/src/llvm_backend_general.cpp +++ b/src/llvm_backend_general.cpp @@ -3033,6 +3033,10 @@ gb_internal void lb_add_attribute_to_proc(lbModule *m, LLVMValueRef proc_value, LLVMAddAttributeAtIndex(proc_value, LLVMAttributeIndex_FunctionIndex, lb_create_enum_attribute(m->ctx, name, value)); } +gb_internal void lb_remove_attribute_from_proc(lbModule *m, LLVMValueRef proc_value, char const *name) { + LLVMRemoveEnumAttributeAtIndex(proc_value, LLVMAttributeIndex_FunctionIndex, LLVMGetEnumAttributeKindForName(name, gb_strlen(name))); +} + gb_internal bool lb_proc_has_attribute(lbModule *m, LLVMValueRef proc_value, char const *name) { LLVMAttributeRef ref = LLVMGetEnumAttributeAtIndex(proc_value, LLVMAttributeIndex_FunctionIndex, LLVMGetEnumAttributeKindForName(name, gb_strlen(name))); return ref != nullptr; diff --git a/src/llvm_backend_proc.cpp b/src/llvm_backend_proc.cpp index 4c7a0fb44..42c2f8653 100644 --- a/src/llvm_backend_proc.cpp +++ b/src/llvm_backend_proc.cpp @@ -213,6 +213,13 @@ gb_internal lbProcedure *lb_create_procedure(lbModule *m, Entity *entity, bool i case ProcedureOptimizationMode_FavorSize: lb_add_attribute_to_proc(m, p->value, "optsize"); break; + default: + // need optsize per proc for -o:size; + // (inliner, unroller, vectorizer, etc check it) + if (build_context.optimization_level == OptimizationLevel_Size) { + lb_add_attribute_to_proc(m, p->value, "optsize"); + } + break; } if (pt->Proc.enable_target_feature.len != 0) { From c41c0fb376da8c76329338bf8776c0987d989143 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 11:01:22 +0100 Subject: [PATCH 14/54] Add non-deterministic flags to x86 --- core/rexcode/isa/riscv/clobber_types.odin | 1 + core/rexcode/isa/x86/clobber_types.odin | 1 + .../isa/x86/tablegen/instruction_table.odin | 26 +++++++++---------- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/core/rexcode/isa/riscv/clobber_types.odin b/core/rexcode/isa/riscv/clobber_types.odin index 6d2b37bbd..3a9c54d98 100644 --- a/core/rexcode/isa/riscv/clobber_types.odin +++ b/core/rexcode/isa/riscv/clobber_types.odin @@ -32,6 +32,7 @@ Side_Effect :: enum u8 { IFENCE, // instruction-fetch synchronization (FENCE.I) ATOMIC, // indivisible memory RMW (AMO*, and the LR/SC pair) RESERVATION, // sets or tests an LR/SC reservation + NONDETERMINISTIC, } Clobber :: struct { diff --git a/core/rexcode/isa/x86/clobber_types.odin b/core/rexcode/isa/x86/clobber_types.odin index 2e2d2eb64..75f72c314 100644 --- a/core/rexcode/isa/x86/clobber_types.odin +++ b/core/rexcode/isa/x86/clobber_types.odin @@ -24,6 +24,7 @@ Side_Effect :: enum u8 { PRIVILEGED, // requires CPL0 / reads-writes supervisor machine state CONTROL, // alters control flow (writes RIP): branches, calls, returns CET, // control-flow-enforcement: landing pads, shadow-stack ops + NONDETERMINISTIC, } Side_Effects :: distinct bit_set[Side_Effect; u16] diff --git a/core/rexcode/isa/x86/tablegen/instruction_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin index 20716bcc8..666c3c791 100644 --- a/core/rexcode/isa/x86/tablegen/instruction_table.odin +++ b/core/rexcode/isa/x86/tablegen/instruction_table.odin @@ -1166,19 +1166,19 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0B, 0, {esc=._0F}}, {side_effects={.TRAP}}}, }, .CPUID = { - {{.CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA2, 0, {esc=._0F}}, {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}}, + {{.CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA2, 0, {esc=._0F}}, {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING, .NONDETERMINISTIC}}}, }, .RDTSC = { - {{.RDTSC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x31, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}}}, + {{.RDTSC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x31, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, side_effects={.NONDETERMINISTIC}}}, }, .RDTSCP = { - {{.RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF9, {esc=._0F}}, {implicit_wr={.RAX, .RCX, .RDX}}}, + {{.RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF9, {esc=._0F}}, {implicit_wr={.RAX, .RCX, .RDX}, side_effects={.NONDETERMINISTIC}}}, }, .RDPMC = { - {{.RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x33, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}}, + {{.RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x33, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.NONDETERMINISTIC}}}, }, .XGETBV = { - {{.XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}}, + {{.XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.NONDETERMINISTIC}}}, }, .XSETBV = { {{.XSETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD1, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}}}, @@ -4647,7 +4647,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {esc=._0F}}, {side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .RDMSR = { - {{.RDMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x32, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}}, + {{.RDMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x32, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED, .NONDETERMINISTIC}}}, }, .WRMSR = { {{.WRMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x30, 0, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}}, @@ -4855,14 +4855,14 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .RDRAND = { - {{.RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, - {{.RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, - {{.RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}}, + {{.RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}}, + {{.RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}}, }, .RDSEED = { - {{.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, - {{.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, - {{.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}}, + {{.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}}, + {{.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}}, }, .SWAPGS = { {{.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF8, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, @@ -4900,7 +4900,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {read={0}, reads_mem=true}}, }, .RDPID = { - {{.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {written={0}}}, + {{.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, }, .WBNOINVD = { {{.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=PREFIX_F3}}, {side_effects={.SERIALIZING, .PRIVILEGED}}}, From 34e7a3bb58205358746761e2ae7e334847c36d93 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 11:02:06 +0100 Subject: [PATCH 15/54] Update binary tables --- .../x86/tablegen/generated/encode_tables.odin | 26 +++++++++--------- .../isa/x86/tables/x86.clobber_forms.bin | Bin 39456 -> 39456 bytes 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 420f18e9d..4cb32cb83 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -4603,15 +4603,15 @@ CLOBBER_FORMS := [2466]lib.Clobber{ // .UD2 {side_effects={.TRAP}}, // .CPUID - {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, + {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING, .NONDETERMINISTIC}}, // .RDTSC - {implicit_wr={.RAX, .RDX}}, + {implicit_wr={.RAX, .RDX}, side_effects={.NONDETERMINISTIC}}, // .RDTSCP - {implicit_wr={.RAX, .RCX, .RDX}}, + {implicit_wr={.RAX, .RCX, .RDX}, side_effects={.NONDETERMINISTIC}}, // .RDPMC - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.NONDETERMINISTIC}}, // .XGETBV - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.NONDETERMINISTIC}}, // .XSETBV {implicit_rd={.RAX, .RCX, .RDX}}, // .CBW @@ -7159,7 +7159,7 @@ CLOBBER_FORMS := [2466]lib.Clobber{ // .RSM {side_effects={.SERIALIZING, .PRIVILEGED}}, // .RDMSR - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED, .NONDETERMINISTIC}}, // .WRMSR {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, // .VMCALL @@ -7302,13 +7302,13 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={1}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .RDRAND - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}, // .RDSEED - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, side_effects={.NONDETERMINISTIC}}, // .SWAPGS {side_effects={.PRIVILEGED}}, // .MONITOR @@ -7335,7 +7335,7 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {read={0}, reads_mem=true}, {read={0}, reads_mem=true}, // .RDPID - {written={0}}, + {written={0}, side_effects={.NONDETERMINISTIC}}, // .WBNOINVD {side_effects={.SERIALIZING, .PRIVILEGED}}, // .SERIALIZE diff --git a/core/rexcode/isa/x86/tables/x86.clobber_forms.bin b/core/rexcode/isa/x86/tables/x86.clobber_forms.bin index 820ee9a2f696777d3c21585ab1116962b3351c6a..c769f15532c6903d9a3f52530a221c011a0e9b6a 100644 GIT binary patch delta 179 zcmZ3mg=xVSrVabG99b9`I2n)tkk5<6WdO?q2^hfOZ_-|$%E+>L!-V@Rfh>$*W%h8z Rl=3G(nED@R_=9N<%mAVj5V!yU delta 164 zcmZ3mg=xVSrVabG3>X*~IDr@$@FH`7Y)%FigvjLoGetMEXs=FXWZ1l6!hIGG21c-? bJzNQy{K Date: Mon, 24 Aug 2026 11:46:07 +0100 Subject: [PATCH 16/54] Add `#pure` directive for `asm` templates --- core/rexcode/isa/riscv/clobber_types.odin | 1 - .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 20 +++- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 22 +++- src/asm_tables_amd64.cpp | 34 ++++-- src/asm_tables_riscv.cpp | 19 ++- src/check_asm.cpp | 108 +++++++++++++++++- src/entity.cpp | 1 + src/parser.cpp | 3 +- 8 files changed, 180 insertions(+), 28 deletions(-) diff --git a/core/rexcode/isa/riscv/clobber_types.odin b/core/rexcode/isa/riscv/clobber_types.odin index 3a9c54d98..6d2b37bbd 100644 --- a/core/rexcode/isa/riscv/clobber_types.odin +++ b/core/rexcode/isa/riscv/clobber_types.odin @@ -32,7 +32,6 @@ Side_Effect :: enum u8 { IFENCE, // instruction-fetch synchronization (FENCE.I) ATOMIC, // indivisible memory RMW (AMO*, and the LR/SC pair) RESERVATION, // sets or tests an LR/SC reservation - NONDETERMINISTIC, } Clobber :: struct { diff --git a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin index 8ab2a4a00..149daecc0 100644 --- a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin @@ -236,6 +236,9 @@ main :: proc() { bool is_conditional() const { return has_control(); } + bool is_nondeterministic() const { + return false; + } }; void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { @@ -273,6 +276,17 @@ main :: proc() { u16 csr; // CSR address when a src slot is AliasSrc_CSR_LIT u8 nargs; // operands the user supplies (ARG0..operands) { + if (op->kind == Ast_AsmLabelDecl) { + saw_label = true; // resolved against label_scope during operand checking + } + } + return saw_label; +} + template gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, @@ -1471,12 +1486,31 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // Handle clobbering from mnemonic auto clobber = clobber_forms[valid_form_index]; + // NOTE(bill): reads_mem/writes_mem are per-FORM capability bits. + // A form with an r/m slot (e.g. add r/m32, imm32) carries them even + // when the operand resolved to a register, e.g. `add x, 123`. + // Count a real access only when an operand actually resolved to memory, + // or the access is implicit (no r/m slot exists to carry the bit: movs/stos/...). + bool has_mem_operand = false; + bool has_rm_slot = false; + auto const &valid_form = forms[valid_form_index]; + for_array(i, operands) { + if (determine_asm_operand_kind(&operands[i]) == AsmOperand_Memory) { + has_mem_operand = true; + } + AsmOperandKind op_kind = asm_ctx->kind_from_operand_type(operand_slot_type(valid_form, cast(int)i)); + if (op_kind == AsmOperand_Memory || op_kind == AsmOperand_Register_Or_Memory) { + has_rm_slot = true; + } + } + bool mem_is_real = has_mem_operand || !has_rm_slot; + tmpl_entity->AsmTemplate.clobber_flags |= clobber.implies_clobber_flags(); - tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); + tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory() && mem_is_real; tmpl_entity->AsmTemplate.is_volatile |= clobber.implies_side_effects(); tmpl_entity->AsmTemplate.has_observable_side_effect |= clobber.implies_side_effects() != 0; - tmpl_entity->AsmTemplate.has_observable_side_effect |= clobber.writes_mem; + tmpl_entity->AsmTemplate.has_observable_side_effect |= clobber.writes_mem && mem_is_real; // #align_stack only matters if the body makes a call (which requires the stack // aligned at the call boundary) or manipulates RSP directly. Plain memory access @@ -1646,6 +1680,39 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } asm_ctx->clobber_implicit_regs(&tmpl_entity->AsmTemplate.clobber_registers_set, produced); + // Purity inference + if (asm_acc->can_be_pure) { + // NOTE(bill): Only the first violating instruction is recorded + // The later ones don't overwrite the reason. + char const *why = nullptr; + + if (clobber.writes_mem && mem_is_real) { + why = "it writes to memory"; + } else if (clobber.reads_mem && mem_is_real) { + // A load's result depends on memory, which is not a value input. + why = "it reads from memory"; + } else if (clobber.is_nondeterministic() || + (pseudo_mnemonic > 0 && alias.is_nondeterministic())) { + // rdtsc / rdrand / cpuid on x86 + // counter/entropy CSR reads on RISC-V. + why = "it is nondeterministic"; + } else if (clobber.implies_clobber_memory() && mem_is_real) { + why = "it accesses memory the compiler cannot see"; + } else if (clobber.implies_side_effects()) { + why = "it has an observable side effect"; + } else if (clobber.has_control() && !check_asm_instr_targets_internal_label(instr)) { + // Internal jmp/jcc/ret over the template's own labels stays pure; a call + // or an indirect/external transfer does not. + why = "it possibly transfers control outside the inline 'asm' template"; + } + + if (why != nullptr) { + asm_acc->can_be_pure = false; + asm_acc->impure_reason = why; + asm_acc->impure_reason_node = instr->name; + } + } + return; } @@ -2188,8 +2255,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity entity->type = type; - bool is_volatile = false; - bool is_align_stack = false; + bool is_volatile = false; + bool is_align_stack = false; + bool is_pure_annotated = false; auto *clobber_registers_set = &entity->AsmTemplate.clobber_registers_set; check_asm_specs(asm_ctx, ctx, ate->param_scope, at->specs, &ate->decls); @@ -2211,6 +2279,11 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity error(clobber->name, "#align_stack has already been defined as an asm specification"); } is_align_stack = true; + } else if (clobber->name.string == "pure") { + if (is_pure_annotated) { + error(clobber->name, "#pure has already been defined as an asm specification"); + } + is_pure_annotated = true; } else { error(clobber->name, "Unknown clobber directive '#%.*s'", LIT(clobber->name.string)); } @@ -2317,6 +2390,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity // jump target / back-edge, after which a read can precede its textual def; from // there on we stop emitting the implicit-read diagnostic. asm_acc.straight_line = true; + asm_acc.can_be_pure = true; // collect label decls for (Ast *instruction_ : at->instructions) { @@ -2657,6 +2731,32 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity "end it with an unconditional jump, return, or halt"); } } + + { + bool declared_effects = entity->AsmTemplate.is_volatile || + entity->AsmTemplate.clobber_memory || + entity->AsmTemplate.has_observable_side_effect; + bool is_pure = asm_acc.can_be_pure && !declared_effects && !type->Proc.diverging; + entity->AsmTemplate.is_pure = is_pure; + + if (is_pure_annotated && !is_pure) { + Ast *node = asm_acc.impure_reason_node; + char const *why = asm_acc.impure_reason; + if (why == nullptr) { + if (type->Proc.diverging) { + why = "it is declared diverging (-> !) and computes no outputs"; + } else if (entity->AsmTemplate.clobber_memory) { + why = "it declares '#clobber memory'"; + } else if (entity->AsmTemplate.is_volatile) { + why = "it is declared '#volatile'"; + } else { + why = "it declares an observable effect"; + } + } + Token tok = node ? ast_token(node): entity->token; + error(tok, "'asm' template is marked #pure but it is not pure: %s", why); + } + } } gb_internal void check_asm_template_from_entity(CheckerContext *c, Entity *e, DeclInfo *d) { diff --git a/src/entity.cpp b/src/entity.cpp index e21ec4483..f6045e341 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -345,6 +345,7 @@ struct Entity { Ast *node; bool is_volatile; bool is_align_stack; + bool is_pure; bool has_observable_side_effect; diff --git a/src/parser.cpp b/src/parser.cpp index d9d07cf57..1173305f8 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2758,7 +2758,8 @@ gb_internal Ast *parse_asm_template(AstFile *f) { Token name = expect_token(f, Token_Ident); if (name.string == "volatile" || - name.string == "align_stack") { + name.string == "align_stack" || + name.string == "pure") { Ast *clobber = alloc_ast_node(f, Ast_AsmClobber); clobber->AsmClobber.token = hash; clobber->AsmClobber.name = name; From 7ebc5c462e7c3d140bd5b2f3cb3b75bf53e4aeea Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 11:57:34 +0100 Subject: [PATCH 17/54] Correct `#pure` checking for internal branches and effect volatility --- src/check_asm.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index cfe2614b2..61e439e76 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1505,11 +1505,15 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } bool mem_is_real = has_mem_operand || !has_rm_slot; + bool internal_branch = clobber.has_control() && check_asm_instr_targets_internal_label(instr); + + bool effective_side_effects = clobber.implies_side_effects() && !internal_branch; + tmpl_entity->AsmTemplate.clobber_flags |= clobber.implies_clobber_flags(); tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory() && mem_is_real; - tmpl_entity->AsmTemplate.is_volatile |= clobber.implies_side_effects(); + tmpl_entity->AsmTemplate.is_volatile |= effective_side_effects; - tmpl_entity->AsmTemplate.has_observable_side_effect |= clobber.implies_side_effects() != 0; + tmpl_entity->AsmTemplate.has_observable_side_effect |= effective_side_effects; tmpl_entity->AsmTemplate.has_observable_side_effect |= clobber.writes_mem && mem_is_real; // #align_stack only matters if the body makes a call (which requires the stack @@ -1698,9 +1702,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm why = "it is nondeterministic"; } else if (clobber.implies_clobber_memory() && mem_is_real) { why = "it accesses memory the compiler cannot see"; - } else if (clobber.implies_side_effects()) { + } else if (effective_side_effects) { why = "it has an observable side effect"; - } else if (clobber.has_control() && !check_asm_instr_targets_internal_label(instr)) { + } else if (!internal_branch && clobber.has_control()) { // Internal jmp/jcc/ret over the template's own labels stays pure; a call // or an indirect/external transfer does not. why = "it possibly transfers control outside the inline 'asm' template"; From 39afdfc6091a390b174da82163d26596711a2509 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 12:13:24 +0100 Subject: [PATCH 18/54] Begin work on improving `#pure` error handling --- core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin | 8 ++++++++ core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin | 7 +++++++ src/asm_tables_amd64.cpp | 7 +++++++ src/asm_tables_riscv.cpp | 8 ++++++++ 4 files changed, 30 insertions(+) diff --git a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin index 149daecc0..e90813937 100644 --- a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin @@ -239,6 +239,14 @@ main :: proc() { bool is_nondeterministic() const { return false; } + bool has_implicit_mem() const { + if (!writes_mem && !reads_mem) { + return false; + } + u16 implicit = cast(u16)implicit_rd | cast(u16)implicit_wr; + bool is_atomic = false; // TODO(bill): Add ATOMIC flag to SideEffectFlags in the original INSTRUCTION_TABLE + return (implicit & (ClobberReg_SP)) != 0 || is_atomic; + } }; void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 346db1b18..27b35a060 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -328,6 +328,13 @@ main :: proc() { bool is_nondeterministic() const { return (cast(u16)side_effects & SideEffectFlag_NONDETERMINISTIC) != 0; } + bool has_implicit_mem() const { + if (!writes_mem && !reads_mem) { + return false; + } + u16 implicit = cast(u16)implicit_rd | cast(u16)implicit_wr; + return (implicit & (ClobberReg_RSP|ClobberReg_RSI|ClobberReg_RDI|ClobberReg_RBX)) != 0; + } }; void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index e518d8524..2a26d4dcd 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -331,6 +331,13 @@ struct Asm_amd64 { bool is_nondeterministic() const { return (cast(u16)side_effects & SideEffectFlag_NONDETERMINISTIC) != 0; } + bool has_implicit_mem() const { + if (!writes_mem && !reads_mem) { + return false; + } + u16 implicit = cast(u16)implicit_rd | cast(u16)implicit_wr; + return (implicit & (ClobberReg_RSP|ClobberReg_RSI|ClobberReg_RDI|ClobberReg_RBX)) != 0; + } }; void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { diff --git a/src/asm_tables_riscv.cpp b/src/asm_tables_riscv.cpp index f5d4156f2..2ffdadd58 100644 --- a/src/asm_tables_riscv.cpp +++ b/src/asm_tables_riscv.cpp @@ -187,6 +187,14 @@ struct Asm_riscv { bool is_nondeterministic() const { return false; } + bool has_implicit_mem() const { + if (!writes_mem && !reads_mem) { + return false; + } + u16 implicit = cast(u16)implicit_rd | cast(u16)implicit_wr; + bool is_atomic = false; // TODO(bill): Add ATOMIC flag to SideEffectFlags in the original INSTRUCTION_TABLE + return (implicit & (ClobberReg_SP)) != 0 || is_atomic; + } }; void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { From 2f588e03293a04f6a66022df0cc0df303d5b7c31 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 12:20:45 +0100 Subject: [PATCH 19/54] Correct clobbering for instructions which did not write actually write to memory --- .../x86/tablegen/generated/encode_tables.odin | 74 +++++++++--------- .../isa/x86/tablegen/instruction_table.odin | 74 +++++++++--------- .../isa/x86/tables/x86.clobber_forms.bin | Bin 39456 -> 39456 bytes src/asm_tables_amd64.cpp | 32 ++++---- src/check_asm.cpp | 2 +- 5 files changed, 91 insertions(+), 91 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 4cb32cb83..08553ef83 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -3724,10 +3724,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={1}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, @@ -3746,8 +3746,8 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, @@ -3810,10 +3810,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, @@ -3830,10 +3830,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, @@ -3850,10 +3850,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, @@ -3870,10 +3870,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, @@ -3958,10 +3958,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, @@ -3978,10 +3978,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, @@ -3998,10 +3998,10 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, @@ -4700,9 +4700,9 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={1}}, {written={0}, read={1}}, // .MOVD + {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLPS {written={0}, read={1}, writes_mem=true, reads_mem=true}, @@ -5434,7 +5434,7 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={1}}, {written={0}, read={1}}, // .VMOVD - {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLPS {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, diff --git a/core/rexcode/isa/x86/tablegen/instruction_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin index 666c3c791..5288651d6 100644 --- a/core/rexcode/isa/x86/tablegen/instruction_table.odin +++ b/core/rexcode/isa/x86/tablegen/instruction_table.odin @@ -87,10 +87,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, {{.MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, {{.MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8A, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8A, 0, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, {{.MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, 0xB0, 0, {}}, {written={0}, read={1}}}, {{.MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, 0xB8, 0, {}}, {written={0}, read={1}}}, {{.MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, 0xB8, 0, {}}, {written={0}, read={1}}}, @@ -109,8 +109,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, {{.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, {{.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, {{.MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F}}, {written={0}, read={1}}}, {{.MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F}}, {written={0}, read={1}}}, {{.MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F}}, {written={0}, read={1}}}, @@ -182,10 +182,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, {{.ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, {{.ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, {{.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, {{.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, {{.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, @@ -203,10 +203,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, {{.ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, {{.ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, + {{.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, + {{.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, + {{.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, {{.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, {{.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, {{.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, @@ -224,10 +224,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, {{.SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, {{.SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, - {{.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, {{.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, {{.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, {{.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, @@ -245,10 +245,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, {{.SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, {{.SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, - {{.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, + {{.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, + {{.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, + {{.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, reads_mem=true}}, {{.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, {{.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, {{.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, @@ -342,10 +342,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, {{.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, {{.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, {{.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, @@ -363,10 +363,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, {{.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, {{.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, {{.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, @@ -384,10 +384,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, - {{.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, {{.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, {{.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, {{.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, @@ -1298,9 +1298,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}}}, }, .MOVD = { - {{.MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, {{.MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, - {{.MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, {{.MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVLPS = { @@ -2352,7 +2352,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, }, .VMOVD = { - {{.VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, {{.VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVLPS = { diff --git a/core/rexcode/isa/x86/tables/x86.clobber_forms.bin b/core/rexcode/isa/x86/tables/x86.clobber_forms.bin index c769f15532c6903d9a3f52530a221c011a0e9b6a..c0b69ba9d43a9ee43d0775aaf444fadb8ee66865 100644 GIT binary patch delta 385 zcmZ3mg=xVSrpXPAzLV!h22AYLpLpiM7s6ML063o!98Pxj&En(W3a0K)9{3}7(X zm-W9P10w?iBQuB(5(RMx@F&-@{imL3o9}Y$XF+m=H3JLCEpSKR;7>lwi|lk9s?bd# nPuFH$fqc2iJT`(8dHF%qnSkNnMlJX8V!(F`&S delta 102 zcmZ3mg=xVSrpW=iJ(F!bOC~X{nQYUPvRQzMhk5cH7L&;VtbZo+u$fG5VEcp2-~51M o56k2jUX#fec>f^Nn+*hV 0) || clobber.has_implicit_mem(); bool internal_branch = clobber.has_control() && check_asm_instr_targets_internal_label(instr); From 805fc078549c801f2fdb80a53b598e3447ab3950 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 14:13:28 +0100 Subject: [PATCH 20/54] Fix indentation of run.sh --- tests/issues/run.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/issues/run.sh b/tests/issues/run.sh index 3e7d4428d..8fffdac59 100755 --- a/tests/issues/run.sh +++ b/tests/issues/run.sh @@ -123,11 +123,11 @@ fi # `asm` templates are amd64-only, so this file is empty on every other architecture if [[ "$(uname -m)" == "x86_64" || "$(uname -m)" == "amd64" ]]; then if [[ $($ODIN check ../test_issue_asm_rip_register.odin -no-entry-point $COMMON_CHECK 2>&1 >/dev/null | grep -c "Error:") -eq 6 ]]; then - echo "SUCCESSFUL 1/1" + echo "SUCCESSFUL 1/1" else echo "SUCCESSFUL 0/1" - exit 1 - fi + exit 1 + fi if [[ $($ODIN check ../test_issue_asm_template_as_value.odin -no-entry-point $COMMON_CHECK 2>&1 >/dev/null | grep -c "Error:") -eq 10 ]]; then echo "SUCCESSFUL 1/1" else From e59da598263eb583ae4fa9f4ced1ef91e5cb13af Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 16:14:25 +0100 Subject: [PATCH 21/54] Add support to check if an output is being read before it is written to; fix `-vet-unused` on input parameters --- src/check_asm.cpp | 105 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 81 insertions(+), 24 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 43a45e5e4..8f99bbabe 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -459,7 +459,7 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope Token name_token = name->Ident.token; Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); - entity->flags |= EntityFlag_Used; + // entity->flags |= EntityFlag_Used; if (is_poly_name) { entity->flags |= EntityFlag_PolyConst; if (is_type_internally_pointer_like(type)) { @@ -552,6 +552,8 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc GB_ASSERT(spec->name->kind == Ast_Ident); Entity *input = scope_lookup_current(scope, spec->name->Ident.interned, spec->name->Ident.hash); + add_entity_use(ctx, spec->name, input); + Entity *other_scratch = nullptr; String pin = {}; @@ -562,6 +564,7 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc if (spec->value->kind == Ast_Ident) { other_scratch = scope_lookup_current(scope, spec->value->Ident.interned, spec->value->Ident.hash); if (other_scratch) { + add_entity_use(ctx, spec->value, other_scratch); auto group = check_asm_find_group(other_scratch, *asm_template_entity_decls, nullptr); if (!group) { error(spec->value, "This must be another parameter, got %.*s", LIT(other_scratch->token.string)); @@ -1058,6 +1061,9 @@ struct AsmMnemonicAccumulator { bool can_be_pure; char const *impure_reason; Ast * impure_reason_node; + + + PtrSet defined_params; }; gb_internal bool check_asm_instr_targets_internal_label(AstAsmInstruction *instr) { @@ -1645,6 +1651,40 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } asm_acc->defined_regs |= produced | pinned_param_writes; + // NOTE(bill): check for read-before-write (use of undefined value) + // Only really meaningful in straight-line code, so a label above means a branch + // could have defined the value out of the textual order + if (asm_acc->straight_line) { + for_array(i, operands) { + auto const &op = operands[i]; + int slot = user_operand_target_index(cast(int)i); + if (slot < 0 || (cast(u16)clobber.read & (1u << slot)) == 0) { + continue; // not a read slot of this form + } + Entity *pe = entity_of_node(op.expr); + if (pe == nullptr || pe->kind != Entity_Variable) { + continue; // literal %reg / immediate / memory, not a tracked param + } + if (!ptr_set_exists(&asm_acc->defined_params, pe)) { + error(op.expr, "'%.*s' reads '%.*s' before it is assigned; its initial value is undefined", + LIT(name), LIT(pe->token.string)); + ptr_set_add(&asm_acc->defined_params, pe); // warn once per param + } + } + } + + // NOTE(bill): record the instruction's parameter writes + for_array(i, operands) { + int slot = user_operand_target_index(cast(int)i); + if (slot < 0 || (cast(u16)clobber.written & (1u << slot)) == 0) { + continue; + } + Entity *pe = entity_of_node(operands[i].expr); + if (pe != nullptr && pe->kind == Entity_Variable) { + ptr_set_add(&asm_acc->defined_params, pe); + } + } + // Registers this form clobbers implicitly (RDTSC->RAX:RDX, etc.), for the // redundant-#clobber hint. Union across the template; pinned regs excluded // so a legitimate output pin is never called "redundant". @@ -2373,19 +2413,29 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } AsmMnemonicAccumulator asm_acc = {}; + ptr_set_init(&asm_acc.defined_params); + defer (ptr_set_destroy(&asm_acc.defined_params)); + // Physical registers known to hold a defined value at the current point in the // straight-line instruction stream. Seeded with input-pinned registers (they // carry their argument at entry); grows as instructions write registers. for (auto const &ed : ate->decls) { - if (ed.pin.len == 0) { - continue; - } - // Only inputs (and the input half of a tie, which is Input-group) hold a - // value at entry. Output/scratch pins start undefined and become defined - // when an instruction writes them. - if (ed.param_group == AsmTemplateEntityDeclParamGroup_Input) { - asm_acc.defined_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); + switch (ed.param_group) { + case AsmTemplateEntityDeclParamGroup_Input: + if (ed.pin.len != 0) { + // Only inputs (and the input half of a tie, which is Input-group) hold a + // value at entry. Output/scratch pins start undefined and become defined + // when an instruction writes them. + asm_acc.defined_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); + } + ptr_set_add(&asm_acc.defined_params, ed.entity); + break; + case AsmTemplateEntityDeclParamGroup_Output: + if (ed.tie >= 0) { + ptr_set_add(&asm_acc.defined_params, ed.entity); + } + break; } } @@ -2605,17 +2655,22 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but the template ended"); } - // for (auto const &ed : ate->decls) { - // if (!(ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.pin.len != 0)) { - // continue; - // } - // u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); - // if (bit && (asm_acc.defined_regs & bit) == 0 && asm_acc.straight_line) { - // error(ed.entity->token, - // "Output '%.*s' is pinned to %%%.*s but nothing in this template writes it", - // LIT(ed.entity->token.string), LIT(ed.pin)); - // } - // } + // TODO(bill): Is this actually correct logic now that the written logic was fixed previously? + for (auto const &ed : ate->decls) { + if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) { + continue; + } + if (ed.pin.len != 0) { + u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); + if (bit != 0 && (asm_acc.defined_regs & bit) == 0 && asm_acc.straight_line) { + error(ed.entity->token, "Output '%.*s' is pinned to %%%.*s but nothing in this template writes it", + LIT(ed.entity->token.string), LIT(ed.pin)); + } + } else if ((ed.entity->flags & EntityFlag_Used) == 0) { + error(ed.entity->token, "Output '%.*s' is unpinned but nothing in this template uses it", + LIT(ed.entity->token.string)); + } + } bool vet_unused = false; @@ -2659,7 +2714,8 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity for (auto const &ed : ate->decls) { bool is_scratch = ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0; bool is_immediate = ed.kind == AsmTemplateEntityDecl_Immediate; - if ((!is_scratch && !is_immediate) || ed.entity == nullptr) { + bool is_input = ed.param_group == AsmTemplateEntityDeclParamGroup_Input; + if ((!is_scratch && !is_immediate && !is_input) || ed.entity == nullptr) { continue; } // Used if its identifier is referenced OR (for a pinned scratch) its pinned @@ -2674,9 +2730,10 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity continue; } } - error(ed.entity->token, "'asm' %s '%.*s' is declared but never used", - is_immediate ? "immediate parameter" : "scratch parameter", - LIT(ed.entity->token.string)); + char const *what = is_immediate ? "immediate" : + is_input ? "input" : + "scratch"; + error(ed.entity->token, "'asm' %s parameter '%.*s' is declared but never used", what, LIT(ed.entity->token.string)); } } From 171bdaf378626cd1e13c951a000f4eb766f18181 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 16:25:00 +0100 Subject: [PATCH 22/54] asm: check for undefined output parameters --- src/check_asm.cpp | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 8f99bbabe..6cdc6c1db 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -2655,20 +2655,27 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but the template ended"); } - // TODO(bill): Is this actually correct logic now that the written logic was fixed previously? for (auto const &ed : ate->decls) { if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) { continue; } + if (ed.tie >= 0) { + continue; + } + if (!asm_acc.straight_line) { + continue; + } + + bool written = false; if (ed.pin.len != 0) { u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); - if (bit != 0 && (asm_acc.defined_regs & bit) == 0 && asm_acc.straight_line) { - error(ed.entity->token, "Output '%.*s' is pinned to %%%.*s but nothing in this template writes it", - LIT(ed.entity->token.string), LIT(ed.pin)); - } - } else if ((ed.entity->flags & EntityFlag_Used) == 0) { - error(ed.entity->token, "Output '%.*s' is unpinned but nothing in this template uses it", - LIT(ed.entity->token.string)); + written = (bit != 0) && (asm_acc.defined_regs & bit) == 0; + } else { + written = ptr_set_exists(&asm_acc.defined_params, ed.entity); + } + + if (!written) { + error(ed.entity->token, "'asm' output parameter '%.*s' is never assigned to in this template, thus its value is undefined", LIT(ed.entity->token.string)); } } From 427d300562ce9ac33c26cbd8f4fb4c59f8ee84dc Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 16:39:23 +0100 Subject: [PATCH 23/54] asm: minor cleanups --- src/check_asm.cpp | 258 ++++++++++++++++++---------------------------- 1 file changed, 103 insertions(+), 155 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 6cdc6c1db..43e68923b 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -7,9 +7,6 @@ gb_internal i32 check_asm_operand_bit_width(Type *type) { if (is_type_untyped(type)) { return -1; } - if (is_type_boolean(type)) { - return 1; - } i64 sz = type_size_of(base_type(type)); if (sz <= 0) { return 0; @@ -85,6 +82,20 @@ gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { return AsmOperand_Invalid; } +gb_internal bool asm_reg_class_compatible(AsmRegClass want, AsmRegClass got) { + switch (want) { + case AsmRegClass_Integer: + return got == AsmRegClass_Integer; + case AsmRegClass_Vector: + // A scalar float uses only the low lane, so it is valid in any vector + // register slot; a #simd vector matches the vector class exactly. + return got == AsmRegClass_Vector || got == AsmRegClass_Float; + case AsmRegClass_Mask: + return got == AsmRegClass_Mask; + } + return true; +} + gb_internal void check_asm_pin_type_compat(AsmRegClass reg_class, i32 reg_w, Type *decl_type, Ast *at, String pin_name, String param_name) { if (reg_class == AsmRegClass_Unknown || @@ -95,14 +106,7 @@ gb_internal void check_asm_pin_type_compat(AsmRegClass reg_class, i32 reg_w, Typ AsmRegClass got_class = check_asm_reg_class_from_type(decl_type); i32 got_w = check_asm_operand_bit_width(decl_type); - bool class_ok; - switch (reg_class) { - case AsmRegClass_Integer: class_ok = (got_class == AsmRegClass_Integer); break; - case AsmRegClass_Vector: class_ok = (got_class == AsmRegClass_Vector || got_class == AsmRegClass_Float); break; - case AsmRegClass_Mask: class_ok = (got_class == AsmRegClass_Mask); break; - default: class_ok = true; break; - } - if (!class_ok) { + if (!!asm_reg_class_compatible(reg_class, got_class)) { error(at, "Parameter '%.*s' is pinned to %%%.*s, but its type is in the wrong register class for that register", LIT(param_name), LIT(pin_name)); return; @@ -304,24 +308,7 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: // must not be held against the slot's register class. Only width matters for the // memory interpretation. Register operands still get the full class check. if (want_class != AsmRegClass_Unknown && !is_memory) { - bool class_ok; - switch (want_class) { - case AsmRegClass_Integer: - class_ok = (got_class == AsmRegClass_Integer); - break; - case AsmRegClass_Vector: - // A scalar float uses only the low lane, so it is valid in any vector - // register slot; a #simd vector matches the vector class exactly. - class_ok = (got_class == AsmRegClass_Vector || got_class == AsmRegClass_Float); - break; - case AsmRegClass_Mask: - class_ok = (got_class == AsmRegClass_Mask); - break; - default: - class_ok = true; - break; - } - if (!class_ok) { + if (!asm_reg_class_compatible(want_class, got_class)) { if (mismatch_) *mismatch_ = AsmMismatch_Class; return false; } @@ -1034,7 +1021,8 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AsmCtx *asm_ctx, AstAsmInstr } struct AsmMnemonicAccumulator { - u16 defined_regs; + u16 defined_regs; + PtrSet defined_params; // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). u16 implicit_clobbered_regs; @@ -1061,9 +1049,6 @@ struct AsmMnemonicAccumulator { bool can_be_pure; char const *impure_reason; Ast * impure_reason_node; - - - PtrSet defined_params; }; gb_internal bool check_asm_instr_targets_internal_label(AstAsmInstruction *instr) { @@ -1083,16 +1068,16 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm u8 previous_prefix, Ast *previous_prefix_instr, AsmMnemonicAccumulator *asm_acc) { GB_ASSERT(mnemonic > 0); - auto forms = asm_ctx->encoding_forms(mnemonic); - auto clobber_forms = asm_ctx->clobber_forms(mnemonic); - String name = asm_ctx->mnemonic_strings[mnemonic]; + auto forms = asm_ctx->encoding_forms(mnemonic); + auto clobber_forms = asm_ctx->clobber_forms(mnemonic); + String name = asm_ctx->mnemonic_strings[mnemonic]; auto alias = asm_ctx->pseudo_alias(cast(u16)pseudo_mnemonic); if (pseudo_mnemonic) { name = asm_ctx->pseudo_mnemonic_strings[pseudo_mnemonic]; } - bool is_pseudo = pseudo_mnemonic != 0; + bool is_pseudo = pseudo_mnemonic != 0; int target_explicit_count = is_pseudo ? alias.nargs : -1; auto form_user_operand_count = [&](typename AsmCtx::Encoding const &form) -> int { @@ -1310,8 +1295,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } error_line("\tPossible forms for '%.*s':\n", LIT(name)); - error_line("\t(r: int, v: vector, f: float, k: mask, m: memory,\n"); - error_line("\t r/m: reg-or-mem, imm: immediate; number: bit=width)\n"); + error_line("\t\t(r: int, v: vector, f: float, k: mask, m: memory,\n"); + error_line("\t\t r/m: reg-or-mem, imm: immediate; number: bit=width)\n"); isize const MAX_SHOWN = 32; isize shown = gb_min(lines.count, MAX_SHOWN); @@ -1382,14 +1367,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm for_array(form_index, forms) { auto &form = forms[form_index]; - if (is_pseudo) { - if (cast(int)form.explicit_count() < target_explicit_count) { - continue; - } - } else { - if (operands.count != cast(int)form.explicit_count()) { - continue; - } + if (is_pseudo && cast(int)form.explicit_count() < target_explicit_count) { + continue; + } else if (operands.count != cast(int)form.explicit_count()) { + continue; } int score = 0; @@ -1405,8 +1386,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm bool kind_ok = (dst == src) || (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); - // Tertiary key: bias toward wider register slots so an r64 form outranks - // an otherwise-equal r32 form. + // Bias toward wider register slots so an r64 form outranks an otherwise-equal r32 form. width_pref += cast(int)asm_ctx->operand_type_bit_width(type); bool spot_ok = false; @@ -1443,7 +1423,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } // Lexicographic rank: score desc, then width_dist asc, then width_pref desc. - bool better; + bool better = false; if (score != best_score) { better = score > best_score; } else if (width_dist != best_dist) { @@ -1736,8 +1716,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // A load's result depends on memory, which is not a value input. why = "it reads from memory"; } else if (clobber.is_nondeterministic() || - (pseudo_mnemonic > 0 && alias.is_nondeterministic())) { - // rdtsc / rdrand / cpuid on x86 + (is_pseudo && alias.is_nondeterministic())) { + // rdtsc/rdrand/cpuid on x86 // counter/entropy CSR reads on RISC-V. why = "it is nondeterministic"; } else if (clobber.implies_clobber_memory() && mem_is_real) { @@ -1760,11 +1740,11 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm return; } - // failure path - enum { MAX_VARIANT_COUNT = 32 }; - AsmMismatch mismatch[MAX_VARIANT_COUNT] = {}; + // NOTE(bill): Failure path + enum { MAX_VARIANT_COUNT = 8 }; + AsmMismatch mismatch [MAX_VARIANT_COUNT] = {}; i32 want_bits[MAX_VARIANT_COUNT] = {}; - i32 got_bits[MAX_VARIANT_COUNT] = {}; + i32 got_bits [MAX_VARIANT_COUNT] = {}; if (best_form >= 0) { auto &form = forms[best_form]; for_array(i, operands) { @@ -1793,82 +1773,80 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } } - { + begin_error_block(); + + bool nearly = best_score >= gb_max(operands.count*2 - 2, 0); + if (nearly) { + error(instr->name, "'%.*s' operands nearly matched the expected encoding forms", LIT(name)); + } else { + error(instr->name, "'%.*s' operands matched none of the expected encoding forms", LIT(name)); + } + + for_array(i, valid_spots) { + if (valid_spots[i] || i >= operands.count) { + continue; + } + auto dst = possible_kinds[i]; + AsmOperandKind src = determine_asm_operand_kind(&operands[i]); + + AsmRegClass dst_reg_class = possible_class_kinds[i]; + AsmRegClass src_reg_class = check_asm_reg_class_from_type(operands[i].type); + + AsmMismatch m = (i < MAX_VARIANT_COUNT) ? mismatch[i] : AsmMismatch_None; + + end_error_block(); begin_error_block(); - bool nearly = best_score >= gb_max(operands.count*2 - 2, 0); - if (nearly) { - error(instr->name, "'%.*s' operands nearly matched the expected encoding forms", LIT(name)); - } else { - error(instr->name, "'%.*s' operands matched none of the expected encoding forms", LIT(name)); - } + if (m == AsmMismatch_ImmRange) { - for_array(i, valid_spots) { - if (valid_spots[i] || i >= operands.count) { - continue; - } - auto dst = possible_kinds[i]; - AsmOperandKind src = determine_asm_operand_kind(&operands[i]); - - AsmRegClass dst_reg_class = possible_class_kinds[i]; - AsmRegClass src_reg_class = check_asm_reg_class_from_type(operands[i].type); - - AsmMismatch m = (i < MAX_VARIANT_COUNT) ? mismatch[i] : AsmMismatch_None; - - end_error_block(); - begin_error_block(); - - if (m == AsmMismatch_ImmRange) { - - ExactValue ev = operands[i].value; - gbString vs = exact_value_to_string(ev); - i32 bits_required = 0; - check_asm_immediate_value_fits(ev, want_bits[i], &bits_required, nullptr); - if (bits_required > 0) { - error(operands[i].expr, "'%.*s' operand-%td is a %d-bit immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", - LIT(name), i, bits_required, vs, cast(int)want_bits[i]); - } else { - error(operands[i].expr, "'%.*s' operand-%td is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", - LIT(name), i, vs, cast(int)want_bits[i]); - } - gb_string_free(vs); - } else if (m == AsmMismatch_ImmType) { - error(operands[i].expr, "'%.*s' operand-%td: a floating-point constant cannot be used as an immediate", - LIT(name), i); - } else if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { - error(operands[i].expr, "'%.*s' operand-%td has the wrong size: expected a %u-bit %.*s operand, got %u-bit", - LIT(name), i, - cast(unsigned)want_bits[i], LIT(asm_reg_class_strings[dst_reg_class]), - cast(unsigned)got_bits[i]); - } else if (m == AsmMismatch_Class) { - error(operands[i].expr, "'%.*s' operand-%td is in the wrong register class, expected %d-bit %.*s %.*s, got %d-bit %.*s %.*s", - LIT(name), i, - want_bits[i], LIT(asm_reg_class_strings[dst_reg_class]), LIT(asm_operand_kind_strings[dst]), - got_bits[i], LIT(asm_reg_class_strings[src_reg_class]), LIT(asm_operand_kind_strings[src])); - } else if (m == AsmMismatch_NamedReg) { - auto slot = operand_slot_type(forms[best_form], cast(int)i); - error(operands[i].expr, "'%.*s' operand-%td must be a named %.*s register, got a %.*s", - LIT(name), i, - LIT(asm_ctx->named_reg_class_string(asm_ctx->operand_type_named_reg_class(slot))), - LIT(asm_operand_kind_strings[src])); - } else if (dst == AsmOperand_Immediate) { - error(operands[i].expr, "'%.*s' operand-%td must be an assemble-time constant or a $ immediate parameter, got a %.*s", - LIT(name), i, LIT(asm_operand_kind_strings[src])); - } else if (dst) { - error(operands[i].expr, "'%.*s' operand-%td has an invalid kind, expected %.*s operand", - LIT(name), i, LIT(asm_operand_kind_expected_strings[dst])); + ExactValue ev = operands[i].value; + gbString vs = exact_value_to_string(ev); + i32 bits_required = 0; + check_asm_immediate_value_fits(ev, want_bits[i], &bits_required, nullptr); + if (bits_required > 0) { + error(operands[i].expr, "'%.*s' operand-%td is a %d-bit immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", + LIT(name), i, bits_required, vs, cast(int)want_bits[i]); } else { - error(operands[i].expr, "'%.*s' operand-%td has an invalid kind", LIT(name), i); + error(operands[i].expr, "'%.*s' operand-%td is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", + LIT(name), i, vs, cast(int)want_bits[i]); } - } - - if (nearly && best_form >= 0) { - print_closest_form(best_form); + gb_string_free(vs); + } else if (m == AsmMismatch_ImmType) { + error(operands[i].expr, "'%.*s' operand-%td: a floating-point constant cannot be used as an immediate", + LIT(name), i); + } else if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { + error(operands[i].expr, "'%.*s' operand-%td has the wrong size: expected a %u-bit %.*s operand, got %u-bit", + LIT(name), i, + cast(unsigned)want_bits[i], LIT(asm_reg_class_strings[dst_reg_class]), + cast(unsigned)got_bits[i]); + } else if (m == AsmMismatch_Class) { + error(operands[i].expr, "'%.*s' operand-%td is in the wrong register class, expected %d-bit %.*s %.*s, got %d-bit %.*s %.*s", + LIT(name), i, + want_bits[i], LIT(asm_reg_class_strings[dst_reg_class]), LIT(asm_operand_kind_strings[dst]), + got_bits[i], LIT(asm_reg_class_strings[src_reg_class]), LIT(asm_operand_kind_strings[src])); + } else if (m == AsmMismatch_NamedReg) { + auto slot = operand_slot_type(forms[best_form], cast(int)i); + error(operands[i].expr, "'%.*s' operand-%td must be a named %.*s register, got a %.*s", + LIT(name), i, + LIT(asm_ctx->named_reg_class_string(asm_ctx->operand_type_named_reg_class(slot))), + LIT(asm_operand_kind_strings[src])); + } else if (dst == AsmOperand_Immediate) { + error(operands[i].expr, "'%.*s' operand-%td must be an assemble-time constant or a $ immediate parameter, got a %.*s", + LIT(name), i, LIT(asm_operand_kind_strings[src])); + } else if (dst) { + error(operands[i].expr, "'%.*s' operand-%td has an invalid kind, expected %.*s operand", + LIT(name), i, LIT(asm_operand_kind_expected_strings[dst])); } else { - print_possible_forms(); + error(operands[i].expr, "'%.*s' operand-%td has an invalid kind", LIT(name), i); } - end_error_block(); } + + if (nearly && best_form >= 0) { + print_closest_form(best_form); + } else { + print_possible_forms(); + } + end_error_block(); } @@ -2720,7 +2698,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity for (auto const &ed : ate->decls) { bool is_scratch = ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0; - bool is_immediate = ed.kind == AsmTemplateEntityDecl_Immediate; + bool is_immediate = ed.kind == AsmTemplateEntityDecl_Immediate; bool is_input = ed.param_group == AsmTemplateEntityDeclParamGroup_Input; if ((!is_scratch && !is_immediate && !is_input) || ed.entity == nullptr) { continue; @@ -2760,36 +2738,6 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity "that would require the stack to be realigned"); } - if (false) { - // TODO(bill): is this even a good idea? The programmer might have just added it for the reason so that he can - // tell if an asm template clobbers something specific or if it is #volatile. - // I'll leave this in an `if (false)` block for the time being just in case it might be useful in the future. - - // Redundant #clobber hint - for (Ast *clobber_ : at->clobbers) { - ast_node(clobber, AsmClobber, clobber_); - if (clobber->value == nullptr || clobber->value->kind != Ast_AsmRegister) { - continue; - } - String reg = clobber->value->AsmRegister.name.string; - u16 bit = asm_ctx->clobber_bit_for_reg_name(reg); - if (bit && (asm_acc.implicit_clobbered_regs & bit) != 0) { - warning(clobber->value, "#clobber %%%.*s is redundant; an instruction in this template already clobbers it implicitly", LIT(reg)); - } - } - - // Redundant #volatile hint - if (entity->AsmTemplate.is_volatile && entity->AsmTemplate.has_observable_side_effect) { - for (Ast *clobber_ : at->clobbers) { - ast_node(clobber, AsmClobber, clobber_); - if (clobber->value == nullptr && clobber->name.string == "volatile") { - warning(clobber->name, "#volatile is redundant; an instruction in this template already has an observable side effect"); - break; - } - } - } - } - if (type->Proc.diverging) { if (!asm_acc.saw_any_instructions) { error(entity->token, "This asm template is declared as diverging (-> !) but its body is empty and cannot diverge"); From 13558978be955f8899e3c2e36814c287efb91a47 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 16:40:02 +0100 Subject: [PATCH 24/54] Fix typo --- src/check_asm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 43e68923b..9a4aef27c 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -2647,7 +2647,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity bool written = false; if (ed.pin.len != 0) { u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); - written = (bit != 0) && (asm_acc.defined_regs & bit) == 0; + written = (bit != 0) && (asm_acc.defined_regs & bit) != 0; } else { written = ptr_set_exists(&asm_acc.defined_params, ed.entity); } From 670b996f91c4083af84397e73e5f492073939deb Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 16:43:36 +0100 Subject: [PATCH 25/54] Minor clean ups --- src/check_asm.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 9a4aef27c..1e9adc310 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -16,7 +16,8 @@ gb_internal i32 check_asm_operand_bit_width(Type *type) { gb_internal bool is_valid_asm_parameter_type(Type *type) { if (is_type_integer(type)) { - return true; + // NOTE(bill): do not allow 128-bit integers + return type_size_of(type) <= 8; } if (is_type_float(type)) { return true; @@ -700,7 +701,6 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc } else { i32 index = -1; auto group = check_asm_find_group(input, *asm_template_entity_decls, &index); - gb_unused(group); GB_ASSERT(index >= 0); auto *i = &(*asm_template_entity_decls)[index]; if (i->pin.len == 0) { @@ -1175,7 +1175,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm s = gb_string_appendc(s, " "); } break; - case AsmOperand_Register: // 1+ chacracters + case AsmOperand_Register: // 1+ characters case AsmOperand_Memory: if (w == 0) { s = gb_string_appendc(s, " "); @@ -1865,8 +1865,6 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * Scope *param_scope = ate->param_scope; Scope *label_scope = ate->label_scope; - gb_unused(param_scope); - gb_unused(label_scope); switch (expr->kind) { case_ast_node(ue, UnaryExpr, expr); @@ -2673,7 +2671,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity Entity *le = entry.value; GB_ASSERT(le != nullptr); if ((le->flags & EntityFlag_Used) == 0) { - error(le->token, "'asm' label '.%.*s' is declared but never reference by any instruction", LIT(le->token.string)); + error(le->token, "'asm' label '.%.*s' is declared but never referenced by any instruction", LIT(le->token.string)); } } } From 9367fa2ec2227965e407654a1e55625e966eaf4c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 16:58:37 +0100 Subject: [PATCH 26/54] Even more general clean ups --- src/check_asm.cpp | 226 ++++++++++++++++++++++------------------------ 1 file changed, 109 insertions(+), 117 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 1e9adc310..7f5a5ab0a 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -384,10 +384,13 @@ gb_internal bool check_asm_addr_register(Operand const *operand, AsmAddrRole rol return false; } if (role == AsmAddr_Index && reg_name.len != 0) { - // rsp/esp cannot be encoded as an index register. - if (reg_name == "rsp" || reg_name == "esp") { - error(operand->expr, "%%%.*s cannot be used as an index register", LIT(reg_name)); - return false; + if (build_context.metrics.arch == TargetArch_amd64) { + // TODO(bill): This is a complete bodge for AMD64, and I need to see if regnalize this further + // rsp/esp cannot be encoded as an index register. + if (reg_name == "rsp" || reg_name == "esp") { + error(operand->expr, "%%%.*s cannot be used as an index register", LIT(reg_name)); + return false; + } } } return true; @@ -447,7 +450,6 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope Token name_token = name->Ident.token; Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); - // entity->flags |= EntityFlag_Used; if (is_poly_name) { entity->flags |= EntityFlag_PolyConst; if (is_type_internally_pointer_like(type)) { @@ -456,33 +458,33 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope } Entity *found = scope_insert(scope, entity); - if (found == nullptr) { - array_add(&variables, entity); - - AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); - if (is_poly_name) { - ed.kind = AsmTemplateEntityDecl_Immediate; - } - if (input_parameters) { - ed.param_group = AsmTemplateEntityDeclParamGroup_Input; - ed.param_index = param_index++; - ed.result_index = -1; - } else { - ed.param_group = AsmTemplateEntityDeclParamGroup_Output; - ed.param_index = -1; - ed.result_index = param_index++; - } - - ed.total_index = cast(i32)asm_template_entity_decls->count; - array_add(asm_template_entity_decls, ed); - } else { + if (found != nullptr) { TokenPos pos = found->token.pos; error(name_token, "Redeclaration of '%.*s' in this scope\n" "\tat %s", LIT(name_token.string), token_pos_to_string(pos)); entity = found; + continue; } + array_add(&variables, entity); + + AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); + if (is_poly_name) { + ed.kind = AsmTemplateEntityDecl_Immediate; + } + if (input_parameters) { + ed.param_group = AsmTemplateEntityDeclParamGroup_Input; + ed.param_index = param_index++; + ed.result_index = -1; + } else { + ed.param_group = AsmTemplateEntityDeclParamGroup_Output; + ed.param_index = -1; + ed.result_index = param_index++; + } + + ed.total_index = cast(i32)asm_template_entity_decls->count; + array_add(asm_template_entity_decls, ed); } } @@ -863,8 +865,8 @@ gb_internal bool check_register(AsmCtx *asm_ctx, Operand *operand, AstAsmRegiste operand->type = alloc_type_simd_vector(16, t_f32); break; default: - GB_PANIC("Unhandled register width size: %d", width_in_bits); - break; + error(asm_reg->name, "%d-bit width asm registers are not supported", width_in_bits); + return false; } return true; @@ -1025,7 +1027,9 @@ struct AsmMnemonicAccumulator { PtrSet defined_params; // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). - u16 implicit_clobbered_regs; + u16 implicit_clobbered_regs; + u16 explicitly_produced_regs; + u16 stale_outputs; bool straight_line; @@ -1037,9 +1041,6 @@ struct AsmMnemonicAccumulator { // Did the template contain any instructions at all? An empty diverging body can't diverge. bool saw_any_instructions; - u16 explicitly_produced_regs; - u16 stale_outputs; - // Related to #align_stack // any call/branch (CONTROL) or memory effect that could require the stack // to be realigned. If none occurred, #align_stack is redundant. @@ -1555,9 +1556,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm LIT(name), rname, role, LIT(owner), rname, LIT(owner)); } else { error(instr->name, - "'%.*s' implicitly reads %%%s, but nothing in this template produces " - "a value for it; pin an input parameter to %%%s, or write %%%s before " - "this instruction", + "'%.*s' implicitly reads %%%s, but nothing in this template produces a value for it; " + "pin an input parameter to %%%s, or write %%%s before this instruction", LIT(name), rname, rname, rname); } } @@ -1576,44 +1576,46 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm auto const &op = operands[i]; Ast *e = op.expr; - if (e && e->kind == Ast_AsmRegister) { + if (e != nullptr && e->kind == Ast_AsmRegister) { u16 b = asm_ctx->clobber_bit_for_reg_name(e->AsmRegister.name.string); produced |= b; explicit_writes |= b; - } else { - // NOTE(bill): A write through a pinned parameter (or a width-view of one) - // defines that parameter's physical register for the read-before-write check only - auto written_pinned_reg_bit = [&](Operand const &op) -> u16 { - Entity *pe = entity_of_node(op.expr); - if (pe == nullptr || pe->kind != Entity_Variable) { - return 0; + continue; + } + + // NOTE(bill): A write through a pinned parameter (or a width-view of one) + // defines that parameter's physical register for the read-before-write check only + auto written_pinned_reg_bit = [&](Operand const &op) -> u16 { + Entity *pe = entity_of_node(op.expr); + if (pe == nullptr || pe->kind != Entity_Variable) { + return 0; + } + auto const &decls = tmpl_entity->AsmTemplate.decls; + for_array(di, decls) { + auto const &ed = decls[di]; + if (ed.entity != pe) { + continue; } - auto const &decls = tmpl_entity->AsmTemplate.decls; - for_array(di, decls) { - auto const &ed = decls[di]; - if (ed.entity != pe) { - continue; + if (ed.pin.len != 0) { + return asm_ctx->clobber_bit_for_reg_name(ed.pin); + } + // NOTE(bill): A width-view carries no pin of its own and thus it aliases its source's register. + if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) { + String src_pin = decls[ed.view_of].pin; + if (src_pin.len != 0) { + return asm_ctx->clobber_bit_for_reg_name(src_pin); } - if (ed.pin.len != 0) { - return asm_ctx->clobber_bit_for_reg_name(ed.pin); - } - // NOTE(bill): A width-view carries no pin of its own and thus it aliases its source's register. - if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) { - String src_pin = decls[ed.view_of].pin; - if (src_pin.len != 0) { - return asm_ctx->clobber_bit_for_reg_name(src_pin); - } - } - return 0; } return 0; - }; + } + return 0; + }; - pinned_param_writes |= written_pinned_reg_bit(operands[i]); - } + pinned_param_writes |= written_pinned_reg_bit(operands[i]); } - if (is_pseudo) { + if (is_pseudo && + build_context.metrics.arch == TargetArch_riscv64) { // Synthesized register sources (e.g. ra in `jal off` -> `jal ra, off`) also // write a physical register; record them so ra is treated as produced/clobbered. u16 synth = 0; @@ -1631,10 +1633,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } asm_acc->defined_regs |= produced | pinned_param_writes; - // NOTE(bill): check for read-before-write (use of undefined value) - // Only really meaningful in straight-line code, so a label above means a branch - // could have defined the value out of the textual order if (asm_acc->straight_line) { + // NOTE(bill): check for read-before-write (use of undefined value) + // Only really meaningful in straight-line code, so a label above means a branch + // could have defined the value out of the textual order for_array(i, operands) { auto const &op = operands[i]; int slot = user_operand_target_index(cast(int)i); @@ -1665,42 +1667,40 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } } - // Registers this form clobbers implicitly (RDTSC->RAX:RDX, etc.), for the - // redundant-#clobber hint. Union across the template; pinned regs excluded - // so a legitimate output pin is never called "redundant". { + // Registers this form clobbers implicitly (RDTSC->RAX:RDX, etc.), for the + // redundant-#clobber hint. Union across the template; pinned regs excluded + // so a legitimate output pin is never called "redundant". u16 implicit_wr = cast(u16)clobber.implicit_wr & asm_ctx->CLOBBER_REGS_NAMED; asm_acc->implicit_clobbered_regs |= implicit_wr & ~pinned_mask; - } - // Approximate staleness. An output that was explicitly produced (literal %reg write) - // and is later implicitly clobbered — without this same instruction re-producing it — - // is marked stale. Explicit re-production clears it. Implicitly-produced outputs - // (RDTSC->RDX) are never tracked, so they never false-fire. - { - u16 implicit_clobber = cast(u16)clobber.implicit_wr & asm_ctx->CLOBBER_REGS_NAMED; + // Approximate staleness. An output that was explicitly produced (literal %reg write) + // and is later implicitly clobbered — without this same instruction re-producing it — + // is marked stale. Explicit re-production clears it. Implicitly-produced outputs + // (RDTSC->RDX) are never tracked, so they never false-fire. asm_acc->explicitly_produced_regs |= explicit_writes; asm_acc->stale_outputs &= ~explicit_writes; - asm_acc->stale_outputs |= implicit_clobber & asm_acc->explicitly_produced_regs & ~explicit_writes; + asm_acc->stale_outputs |= implicit_wr & asm_acc->explicitly_produced_regs & ~explicit_writes; } - // Terminality for a #diverging template: this instruction ends straight-line - // flow off the end (jmp/ret/etc. -> CONTROL, hlt/ud2 -> HALT). A conditional - // branch does NOT terminate (it can fall through), so require that the form - // is not merely CONTROL-with-fallthrough. We approximate "unconditional" as - // CONTROL|HALT with no explicit label/operand fallthrough below. { + // Terminality for a #diverging template: this instruction ends straight-line + // flow off the end (jmp/ret/etc. -> CONTROL, hlt/ud2 -> HALT). A conditional + // branch does NOT terminate (it can fall through), so require that the form + // is not merely CONTROL-with-fallthrough. We approximate "unconditional" as + // CONTROL|HALT with no explicit label/operand fallthrough below. + bool control = clobber.has_control(); bool halt = clobber.has_halt(); // A conditional branch reads a flag and can fall through -> not terminal. bool conditional = clobber.is_conditional(); asm_acc->last_is_terminal = halt || (control && !conditional); - } - // A branch/call inside the template means subsequent instructions may be reached - // out of textual order; stop trusting the linear def model past this point. - if (clobber.has_control()) { - asm_acc->straight_line = false; + if (control) { + // A branch/call inside the template means subsequent instructions may be reached + // out of textual order; stop trusting the linear def model past this point. + asm_acc->straight_line = false; + } } asm_ctx->clobber_implicit_regs(&tmpl_entity->AsmTemplate.clobber_registers_set, produced); @@ -1751,11 +1751,13 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm auto type = operand_slot_type(form, cast(int)i); AsmOperandKind dst = asm_ctx->kind_from_operand_type(type); AsmOperandKind src = determine_asm_operand_kind(&operands[i]); - possible_kinds[i] = dst; + + possible_kinds [i] = dst; possible_class_kinds[i] = asm_ctx->reg_class_from_operand_type(type); bool kind_ok = (dst == src) || - (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); + (dst == AsmOperand_Register_Or_Memory + && (src == AsmOperand_Register || src == AsmOperand_Memory)); if (!kind_ok) { valid_spots[i] = false; } else { @@ -1798,7 +1800,6 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm begin_error_block(); if (m == AsmMismatch_ImmRange) { - ExactValue ev = operands[i].value; gbString vs = exact_value_to_string(ev); i32 bits_required = 0; @@ -1893,20 +1894,22 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * return; } found = scope_lookup(param_scope->parent, i->interned, i->hash); - if (found != nullptr) { - if (found->kind == Entity_Constant) { - i->entity = found; - operand->mode = Addressing_Constant; - operand->value = found->Constant.value; - operand->type = found->type; - - add_type_and_value(ctx, expr, operand->mode, operand->type, operand->value); - } else { - error(expr, "Only asm parameters or constants are allowed to be used within an 'asm' template"); - } - } else { + if (found == nullptr) { error(expr, "Undeclared asm parameter or constant '%.*s'", LIT(i->token.string)); + return; } + + if (found->kind != Entity_Constant) { + error(expr, "Only asm parameters or constants are allowed to be used within an 'asm' template"); + return; + } + + add_entity_use(ctx, expr, entity); + operand->mode = Addressing_Constant; + operand->value = found->Constant.value; + operand->type = found->type; + + add_type_and_value(ctx, expr, operand->mode, operand->type, operand->value); return; case_end; case_ast_node(bl, BasicLit, expr); @@ -2221,12 +2224,10 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * Entity *found = scope_lookup_current(label_scope, name->interned, name->hash); if (found == nullptr) { error(expr, "Undeclared asm label '.%.*s'", LIT(name->token.string)); + return; } - name->entity = found; - if (found != nullptr) { - found->flags |= EntityFlag_Used; - add_type_and_value(ctx, expr, Addressing_Value, found->type, {}); - } + add_entity_use(ctx, label->name, found); + add_type_and_value(ctx, expr, Addressing_Value, found->type, {}); return; case_end; } @@ -2544,21 +2545,12 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity check_asm_instruction_operand(asm_ctx, ctx, entity, &operand, expr, /*allow_memory_operands*/true); array_add(&operands, operand); } - for (auto const &op : operands) { + for (auto &op : operands) { if (op.mode != Addressing_Constant) { error(op.expr, "Expected an integer for the asm directive #%.*s", LIT(name)); continue; } - ExactValue ev = exact_value_to_integer(op.value); - if (ev.kind != ExactValue_Integer) { - error(op.expr, "Expected an integer for the asm directive #%.*s", LIT(name)); - continue; - } - i64 i = exact_value_to_i64(ev); - if (i < 0 || i > 255) { - error(op.expr, "Expected an integer within 0..<256 for the asm directive #%.*s, got %lld", LIT(name), cast(long long)i); - continue; - } + check_assignment(ctx, &op, t_u8, str_lit("asm '#byte' directive")); } } else if (name == "align") { if (dir->operands.count != 1) { From 9ae9a9bf995b86c3b67334edd0fbf18a028c7170 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 18:18:28 +0100 Subject: [PATCH 27/54] asm: Add support for constraint checks such as division by zero or overshifting --- .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 16 + core/rexcode/isa/x86/mnemonics.odin | 1 + .../x86/tablegen/cpp-compiler/cpp-gen.odin | 17 + .../x86/tablegen/generated/decode_tables.odin | 1276 ++++----- .../x86/tablegen/generated/encode_tables.odin | 2455 +++++++++-------- .../isa/x86/tablegen/instruction_table.odin | 14 + .../isa/x86/tables/x86.clobber_forms.bin | Bin 39456 -> 39648 bytes .../isa/x86/tables/x86.encode_forms.bin | Bin 39456 -> 39648 bytes .../isa/x86/tables/x86.encode_recipes.bin | Bin 29592 -> 29736 bytes .../isa/x86/tables/x86.encode_runs.bin | Bin 9928 -> 9936 bytes core/rexcode/isa/x86/tables/x86.evex.bin | Bin 8420 -> 8420 bytes core/rexcode/isa/x86/tables/x86.idx_0f.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.idx_0f38.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.idx_0f3a.bin | Bin 4096 -> 4096 bytes .../rexcode/isa/x86/tables/x86.idx_legacy.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.legacy.bin | Bin 26760 -> 27000 bytes core/rexcode/isa/x86/tables/x86.vex.bin | Bin 14140 -> 14140 bytes src/asm_tables.cpp | 14 + src/asm_tables_amd64.cpp | 1564 +++++------ src/asm_tables_riscv.cpp | 11 + src/check_asm.cpp | 62 +- 21 files changed, 2809 insertions(+), 2621 deletions(-) diff --git a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin index e90813937..dbd9a4ca5 100644 --- a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin @@ -805,6 +805,22 @@ main :: proc() { } """) + strings.write_string(&sb, "\n") + + strings.write_string(&sb, """ + AsmOperandConstraint operand_value_constraint(u16 m, int op) const { + switch (m) { + case M_SLLI: case M_SRLI: case M_SRAI: + if (op == 2) return {AsmOperandConstraint_ShiftCount, /*XLEN*/-1}; + break; + case M_DIV: case M_DIVU: case M_REM: case M_REMU: + if (op == 2) return {AsmOperandConstraint_NonZeroDivisor, -1}; + break; + } + return {AsmOperandConstraint_None, -1}; + } + """) + strings.write_string(&sb, "\n};\n") strings.write_string(&sb, "\n\n\n") diff --git a/core/rexcode/isa/x86/mnemonics.odin b/core/rexcode/isa/x86/mnemonics.odin index c6b429ec6..3841bfb76 100644 --- a/core/rexcode/isa/x86/mnemonics.odin +++ b/core/rexcode/isa/x86/mnemonics.odin @@ -53,6 +53,7 @@ Mnemonic :: enum u16 { SHL, SHR, SAR, + SAL, ROL, ROR, RCL, diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 27b35a060..084f0acff 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -807,6 +807,23 @@ main :: proc() { } """) + strings.write_string(&sb, "\n") + + strings.write_string(&sb, """ + AsmOperandConstraint operand_value_constraint(u16 m, int op) const { + switch (m) { + case M_SHL: case M_SHR: case M_SAR: case M_SAL: + case M_ROL: case M_ROR: case M_RCL: case M_RCR: + if (op == 1) return {AsmOperandConstraint_ShiftCount, /*width_operand*/0}; + break; + case M_DIV: case M_IDIV: + if (op == 0) return {AsmOperandConstraint_NonZeroDivisor, -1}; + break; + } + return {AsmOperandConstraint_None, -1}; + } + """) + strings.write_string(&sb, "\n};\n") strings.write_string(&sb, "\n\n\n") diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index 17569f005..7dec7ce02 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -144,55 +144,55 @@ SIB_TABLE := [256]lib.SIB_Info{ } @(rodata) -LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ +LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, @@ -202,9 +202,9 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x24, 0xFF, .AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, @@ -218,9 +218,9 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, @@ -231,33 +231,33 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, - {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, - {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, @@ -265,33 +265,33 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x77, 0xFF, .JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x78, 0xFF, .JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x02, .ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -303,9 +303,9 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -313,8 +313,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -327,9 +327,9 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -342,16 +342,16 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, @@ -373,24 +373,24 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, + {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, + {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, - {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, + {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, @@ -409,35 +409,35 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, + {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, @@ -448,29 +448,33 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xC0, 0x02, .RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x03, .RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x04, .SAL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x03, .RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x03, .RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SAL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SAL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SAL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x04, .SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x07, .SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC2, 0xFF, .RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xC3, 0xFF, .RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xC6, 0x00, .MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -483,27 +487,31 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x03, .RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x04, .SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x04, .SAL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x05, .SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x07, .SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x00, .ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x01, .ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x02, .RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x03, .RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SAL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SAL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SAL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -517,21 +525,25 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xD2, 0x01, .ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x02, .RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x03, .RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x04, .SAL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x04, .SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x05, .SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x07, .SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x01, .ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x01, .ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x02, .RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x02, .RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SAL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SAL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SAL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x04, .SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -565,10 +577,10 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0x03, .FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xC0, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xD9, 0xC8, .FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xD9, 0xC9, .FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, @@ -623,8 +635,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xDB, 0xC8, .FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xD0, .FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xD8, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xDB, 0xE2, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE2, .FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDB, 0xE2, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE3, .FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE3, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE8, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, @@ -648,8 +660,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xDD, 0x02, .FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x03, .FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0xC0, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -697,12 +709,12 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xE0, 0xFF, .LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE1, 0xFF, .LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE2, 0xFF, .LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {force_rex_w=true, op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE4, 0xFF, .IN, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xE5, 0xFF, .IN, {.AX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE5, 0xFF, .IN, {.EAX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xE5, 0xFF, .IN, {.AX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE6, 0xFF, .OUT, {.IMM8, .AL_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .AX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .EAX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {op_count=2}}, @@ -710,8 +722,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xE9, 0xFF, .JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xEB, 0xFF, .JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xEC, 0xFF, .IN, {.AL_IMPL, .DX_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xED, 0xFF, .IN, {.EAX_IMPL, .DX_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xED, 0xFF, .IN, {.AX_IMPL, .DX_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, + {.NONE, 0, 0xED, 0xFF, .IN, {.EAX_IMPL, .DX_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xEE, 0xFF, .OUT, {.DX_IMPL, .AL_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xEF, 0xFF, .OUT, {.DX_IMPL, .EAX_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xEF, 0xFF, .OUT, {.DX_IMPL, .AX_IMPL, .NONE, .NONE}, {.IMPL, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, @@ -761,37 +773,37 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {.NONE, 0, 0xFF, 0x01, .DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x02, .CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x04, .JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x02, .LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x05, .VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x00, .SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0xC0, .ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -829,12 +841,12 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0x01, 0xFD, .RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFE, .INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x05, 0xFF, .SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x06, 0xFF, .CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x07, 0xFF, .SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -845,13 +857,13 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x13, 0xFF, .MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x14, 0xFF, .UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x15, 0xFF, .UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x17, 0xFF, .MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x18, 0x00, .PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x01, .PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -876,96 +888,96 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0x33, 0xFF, .RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x34, 0xFF, .SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x35, 0xFF, .SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x40, 0xFF, .CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x48, 0xFF, .CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -992,18 +1004,18 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0x7F, 0xFF, .MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x80, 0xFF, .JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x81, 0xFF, .JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x82, 0xFF, .JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x83, 0xFF, .JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x83, 0xFF, .JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x83, 0xFF, .JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x84, 0xFF, .JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x84, 0xFF, .JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x85, 0xFF, .JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x86, 0xFF, .JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x87, 0xFF, .JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x87, 0xFF, .JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x88, 0xFF, .JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, @@ -1016,15 +1028,15 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0x8C, 0xFF, .JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8D, 0xFF, .JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8D, 0xFF, .JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8E, 0xFF, .JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8F, 0xFF, .JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8F, 0xFF, .JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x90, 0xFF, .SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x91, 0xFF, .SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x92, 0xFF, .SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x92, 0xFF, .SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x93, 0xFF, .SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x93, 0xFF, .SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x93, 0xFF, .SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, @@ -1038,8 +1050,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0x97, 0xFF, .SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x98, 0xFF, .SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x99, 0xFF, .SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9A, 0xFF, .SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9B, 0xFF, .SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9B, 0xFF, .SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9C, 0xFF, .SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, @@ -1059,29 +1071,29 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA8, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA9, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xAA, 0xFF, .RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAB, 0xFF, .BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAB, 0xFF, .BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x01, .FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x04, .XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x07, .CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1092,8 +1104,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0xAF, 0xFF, .IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, @@ -1104,56 +1116,56 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB9, 0xFF, .UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x04, .BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x04, .BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x06, .BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x07, .BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBB, 0xFF, .BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBC, 0xFF, .BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBC, 0xFF, .BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBD, 0xFF, .BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=1}}, + {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 1, 0x10, 0xFF, .MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x11, 0xFF, .MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1197,8 +1209,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 1, 0x6B, 0xFF, .PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6C, 0xFF, .PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6D, 0xFF, .PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6F, 0xFF, .MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x70, 0xFF, .PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x71, 0x02, .PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -1214,15 +1226,15 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 1, 0x76, 0xFF, .PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7C, 0xFF, .HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7D, 0xFF, .HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xAE, 0x07, .CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC6, 0xFF, .SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, @@ -1234,8 +1246,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 1, 0xD4, 0xFF, .PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xD5, 0xFF, .PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xD6, 0xFF, .MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0xD8, 0xFF, .PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xD9, 0xFF, .PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xDA, 0xFF, .PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1285,14 +1297,14 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0xFA, .ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x1E, 0xFB, .ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x51, 0xFF, .SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, @@ -1320,19 +1332,19 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x06, .UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xC7, 0x07, .RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1344,8 +1356,8 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x51, 0xFF, .SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1371,15 +1383,15 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F38, 0, 0xCC, 0xFF, .SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xCD, 0xFF, .SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xFC, 0xFF, .AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xFC, 0xFF, .AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x00, 0xFF, .PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, @@ -1437,26 +1449,26 @@ LEGACY_DECODE_ENTRIES := [1338]lib.Decode_Entry{ {._0F38, 1, 0xDD, 0xFF, .AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDE, 0xFF, .AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDF, 0xFF, .AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF8, 0xFF, .MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0xFC, 0xFF, .AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xFC, 0xFF, .AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xFC, 0xFF, .AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF8, 0xFF, .ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, - {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF8, 0xFF, .ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xFC, 0xFF, .AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xFC, 0xFF, .AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xFC, 0xFF, .AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x08, 0xFF, .ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x09, 0xFF, .ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, @@ -2739,64 +2751,64 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ 0xAF = { 290, 3}, 0xB0 = { 293, 1}, 0xB8 = { 294, 4}, - 0xC0 = { 298, 7}, - 0xC1 = { 305, 21}, - 0xC2 = { 326, 1}, - 0xC3 = { 327, 1}, - 0xC6 = { 328, 1}, - 0xC7 = { 329, 3}, - 0xC8 = { 332, 1}, - 0xC9 = { 333, 1}, - 0xCC = { 334, 1}, - 0xCD = { 335, 1}, - 0xCE = { 336, 1}, - 0xCF = { 337, 3}, - 0xD0 = { 340, 7}, - 0xD1 = { 347, 21}, - 0xD2 = { 368, 7}, - 0xD3 = { 375, 21}, - 0xD7 = { 396, 2}, - 0xD8 = { 398, 18}, - 0xD9 = { 416, 40}, - 0xDA = { 456, 13}, - 0xDB = { 469, 16}, - 0xDC = { 485, 14}, - 0xDD = { 499, 16}, - 0xDE = { 515, 21}, - 0xDF = { 536, 13}, - 0xE0 = { 549, 1}, - 0xE1 = { 550, 1}, - 0xE2 = { 551, 1}, - 0xE3 = { 552, 3}, - 0xE4 = { 555, 1}, - 0xE5 = { 556, 2}, - 0xE6 = { 558, 1}, - 0xE7 = { 559, 2}, - 0xE8 = { 561, 1}, - 0xE9 = { 562, 1}, - 0xEB = { 563, 1}, - 0xEC = { 564, 1}, - 0xED = { 565, 2}, - 0xEE = { 567, 1}, - 0xEF = { 568, 2}, - 0xF0 = { 570, 1}, - 0xF4 = { 571, 1}, - 0xF5 = { 572, 1}, - 0xF6 = { 573, 7}, - 0xF7 = { 580, 21}, - 0xF8 = { 601, 1}, - 0xF9 = { 602, 1}, - 0xFA = { 603, 1}, - 0xFB = { 604, 1}, - 0xFC = { 605, 1}, - 0xFD = { 606, 1}, - 0xFE = { 607, 2}, - 0xFF = { 609, 16}, + 0xC0 = { 298, 8}, + 0xC1 = { 306, 24}, + 0xC2 = { 330, 1}, + 0xC3 = { 331, 1}, + 0xC6 = { 332, 1}, + 0xC7 = { 333, 3}, + 0xC8 = { 336, 1}, + 0xC9 = { 337, 1}, + 0xCC = { 338, 1}, + 0xCD = { 339, 1}, + 0xCE = { 340, 1}, + 0xCF = { 341, 3}, + 0xD0 = { 344, 8}, + 0xD1 = { 352, 24}, + 0xD2 = { 376, 8}, + 0xD3 = { 384, 24}, + 0xD7 = { 408, 2}, + 0xD8 = { 410, 18}, + 0xD9 = { 428, 40}, + 0xDA = { 468, 13}, + 0xDB = { 481, 16}, + 0xDC = { 497, 14}, + 0xDD = { 511, 16}, + 0xDE = { 527, 21}, + 0xDF = { 548, 13}, + 0xE0 = { 561, 1}, + 0xE1 = { 562, 1}, + 0xE2 = { 563, 1}, + 0xE3 = { 564, 3}, + 0xE4 = { 567, 1}, + 0xE5 = { 568, 2}, + 0xE6 = { 570, 1}, + 0xE7 = { 571, 2}, + 0xE8 = { 573, 1}, + 0xE9 = { 574, 1}, + 0xEB = { 575, 1}, + 0xEC = { 576, 1}, + 0xED = { 577, 2}, + 0xEE = { 579, 1}, + 0xEF = { 580, 2}, + 0xF0 = { 582, 1}, + 0xF4 = { 583, 1}, + 0xF5 = { 584, 1}, + 0xF6 = { 585, 7}, + 0xF7 = { 592, 21}, + 0xF8 = { 613, 1}, + 0xF9 = { 614, 1}, + 0xFA = { 615, 1}, + 0xFB = { 616, 1}, + 0xFC = { 617, 1}, + 0xFD = { 618, 1}, + 0xFE = { 619, 2}, + 0xFF = { 621, 16}, }, { // prefix = 66 }, { // prefix = F3 - 0x90 = { 625, 1}, + 0x90 = { 637, 1}, }, { // prefix = F2 }, @@ -2805,434 +2817,434 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ @(rodata) DECODE_INDEX_ESC_0F := [4][256]lib.Decode_Index{ { // prefix = none - 0x00 = { 626, 10}, - 0x01 = { 636, 48}, - 0x02 = { 684, 3}, - 0x03 = { 687, 3}, - 0x05 = { 690, 1}, - 0x06 = { 691, 1}, - 0x07 = { 692, 1}, - 0x08 = { 693, 1}, - 0x09 = { 694, 1}, - 0x0B = { 695, 1}, - 0x0D = { 696, 2}, - 0x10 = { 698, 1}, - 0x11 = { 699, 1}, - 0x12 = { 700, 2}, - 0x13 = { 702, 1}, - 0x14 = { 703, 1}, - 0x15 = { 704, 1}, - 0x16 = { 705, 2}, - 0x17 = { 707, 1}, - 0x18 = { 708, 4}, - 0x1C = { 712, 1}, - 0x1F = { 713, 3}, - 0x20 = { 716, 1}, - 0x21 = { 717, 1}, - 0x22 = { 718, 1}, - 0x23 = { 719, 1}, - 0x28 = { 720, 1}, - 0x29 = { 721, 1}, - 0x2B = { 722, 1}, - 0x2E = { 723, 1}, - 0x2F = { 724, 1}, - 0x30 = { 725, 1}, - 0x31 = { 726, 1}, - 0x32 = { 727, 1}, - 0x33 = { 728, 1}, - 0x34 = { 729, 1}, - 0x35 = { 730, 1}, - 0x40 = { 731, 3}, - 0x41 = { 734, 3}, - 0x42 = { 737, 9}, - 0x43 = { 746, 9}, - 0x44 = { 755, 6}, - 0x45 = { 761, 6}, - 0x46 = { 767, 6}, - 0x47 = { 773, 6}, - 0x48 = { 779, 3}, - 0x49 = { 782, 3}, - 0x4A = { 785, 6}, - 0x4B = { 791, 6}, - 0x4C = { 797, 6}, - 0x4D = { 803, 6}, - 0x4E = { 809, 6}, - 0x4F = { 815, 6}, - 0x50 = { 821, 2}, - 0x51 = { 823, 1}, - 0x52 = { 824, 1}, - 0x53 = { 825, 1}, - 0x54 = { 826, 1}, - 0x55 = { 827, 1}, - 0x56 = { 828, 1}, - 0x57 = { 829, 1}, - 0x58 = { 830, 1}, - 0x59 = { 831, 1}, - 0x5A = { 832, 1}, - 0x5B = { 833, 1}, - 0x5C = { 834, 1}, - 0x5D = { 835, 1}, - 0x5E = { 836, 1}, - 0x5F = { 837, 1}, - 0x6E = { 838, 1}, - 0x6F = { 839, 1}, - 0x70 = { 840, 1}, - 0x78 = { 841, 1}, - 0x79 = { 842, 1}, - 0x7E = { 843, 1}, - 0x7F = { 844, 1}, - 0x80 = { 845, 1}, - 0x81 = { 846, 1}, - 0x82 = { 847, 3}, - 0x83 = { 850, 3}, - 0x84 = { 853, 2}, - 0x85 = { 855, 2}, - 0x86 = { 857, 2}, - 0x87 = { 859, 2}, - 0x88 = { 861, 1}, - 0x89 = { 862, 1}, - 0x8A = { 863, 2}, - 0x8B = { 865, 2}, - 0x8C = { 867, 2}, - 0x8D = { 869, 2}, - 0x8E = { 871, 2}, - 0x8F = { 873, 2}, - 0x90 = { 875, 1}, - 0x91 = { 876, 1}, - 0x92 = { 877, 3}, - 0x93 = { 880, 3}, - 0x94 = { 883, 2}, - 0x95 = { 885, 2}, - 0x96 = { 887, 2}, - 0x97 = { 889, 2}, - 0x98 = { 891, 1}, - 0x99 = { 892, 1}, - 0x9A = { 893, 2}, - 0x9B = { 895, 2}, - 0x9C = { 897, 2}, - 0x9D = { 899, 2}, - 0x9E = { 901, 2}, - 0x9F = { 903, 2}, - 0xA0 = { 905, 1}, - 0xA1 = { 906, 1}, - 0xA2 = { 907, 1}, - 0xA3 = { 908, 3}, - 0xA4 = { 911, 3}, - 0xA5 = { 914, 3}, - 0xA8 = { 917, 1}, - 0xA9 = { 918, 1}, - 0xAA = { 919, 1}, - 0xAB = { 920, 3}, - 0xAC = { 923, 3}, - 0xAD = { 926, 3}, - 0xAE = { 929, 14}, - 0xAF = { 943, 3}, - 0xB0 = { 946, 1}, - 0xB1 = { 947, 3}, - 0xB3 = { 950, 3}, - 0xB6 = { 953, 3}, - 0xB7 = { 956, 2}, - 0xB9 = { 958, 1}, - 0xBA = { 959, 12}, - 0xBB = { 971, 3}, - 0xBC = { 974, 3}, - 0xBD = { 977, 3}, - 0xBE = { 980, 3}, - 0xBF = { 983, 2}, - 0xC0 = { 985, 1}, - 0xC1 = { 986, 3}, - 0xC2 = { 989, 1}, - 0xC6 = { 990, 1}, - 0xC7 = { 991, 16}, - 0xC8 = {1007, 2}, - 0xFF = {1009, 1}, + 0x00 = { 638, 10}, + 0x01 = { 648, 48}, + 0x02 = { 696, 3}, + 0x03 = { 699, 3}, + 0x05 = { 702, 1}, + 0x06 = { 703, 1}, + 0x07 = { 704, 1}, + 0x08 = { 705, 1}, + 0x09 = { 706, 1}, + 0x0B = { 707, 1}, + 0x0D = { 708, 2}, + 0x10 = { 710, 1}, + 0x11 = { 711, 1}, + 0x12 = { 712, 2}, + 0x13 = { 714, 1}, + 0x14 = { 715, 1}, + 0x15 = { 716, 1}, + 0x16 = { 717, 2}, + 0x17 = { 719, 1}, + 0x18 = { 720, 4}, + 0x1C = { 724, 1}, + 0x1F = { 725, 3}, + 0x20 = { 728, 1}, + 0x21 = { 729, 1}, + 0x22 = { 730, 1}, + 0x23 = { 731, 1}, + 0x28 = { 732, 1}, + 0x29 = { 733, 1}, + 0x2B = { 734, 1}, + 0x2E = { 735, 1}, + 0x2F = { 736, 1}, + 0x30 = { 737, 1}, + 0x31 = { 738, 1}, + 0x32 = { 739, 1}, + 0x33 = { 740, 1}, + 0x34 = { 741, 1}, + 0x35 = { 742, 1}, + 0x40 = { 743, 3}, + 0x41 = { 746, 3}, + 0x42 = { 749, 9}, + 0x43 = { 758, 9}, + 0x44 = { 767, 6}, + 0x45 = { 773, 6}, + 0x46 = { 779, 6}, + 0x47 = { 785, 6}, + 0x48 = { 791, 3}, + 0x49 = { 794, 3}, + 0x4A = { 797, 6}, + 0x4B = { 803, 6}, + 0x4C = { 809, 6}, + 0x4D = { 815, 6}, + 0x4E = { 821, 6}, + 0x4F = { 827, 6}, + 0x50 = { 833, 2}, + 0x51 = { 835, 1}, + 0x52 = { 836, 1}, + 0x53 = { 837, 1}, + 0x54 = { 838, 1}, + 0x55 = { 839, 1}, + 0x56 = { 840, 1}, + 0x57 = { 841, 1}, + 0x58 = { 842, 1}, + 0x59 = { 843, 1}, + 0x5A = { 844, 1}, + 0x5B = { 845, 1}, + 0x5C = { 846, 1}, + 0x5D = { 847, 1}, + 0x5E = { 848, 1}, + 0x5F = { 849, 1}, + 0x6E = { 850, 1}, + 0x6F = { 851, 1}, + 0x70 = { 852, 1}, + 0x78 = { 853, 1}, + 0x79 = { 854, 1}, + 0x7E = { 855, 1}, + 0x7F = { 856, 1}, + 0x80 = { 857, 1}, + 0x81 = { 858, 1}, + 0x82 = { 859, 3}, + 0x83 = { 862, 3}, + 0x84 = { 865, 2}, + 0x85 = { 867, 2}, + 0x86 = { 869, 2}, + 0x87 = { 871, 2}, + 0x88 = { 873, 1}, + 0x89 = { 874, 1}, + 0x8A = { 875, 2}, + 0x8B = { 877, 2}, + 0x8C = { 879, 2}, + 0x8D = { 881, 2}, + 0x8E = { 883, 2}, + 0x8F = { 885, 2}, + 0x90 = { 887, 1}, + 0x91 = { 888, 1}, + 0x92 = { 889, 3}, + 0x93 = { 892, 3}, + 0x94 = { 895, 2}, + 0x95 = { 897, 2}, + 0x96 = { 899, 2}, + 0x97 = { 901, 2}, + 0x98 = { 903, 1}, + 0x99 = { 904, 1}, + 0x9A = { 905, 2}, + 0x9B = { 907, 2}, + 0x9C = { 909, 2}, + 0x9D = { 911, 2}, + 0x9E = { 913, 2}, + 0x9F = { 915, 2}, + 0xA0 = { 917, 1}, + 0xA1 = { 918, 1}, + 0xA2 = { 919, 1}, + 0xA3 = { 920, 3}, + 0xA4 = { 923, 3}, + 0xA5 = { 926, 3}, + 0xA8 = { 929, 1}, + 0xA9 = { 930, 1}, + 0xAA = { 931, 1}, + 0xAB = { 932, 3}, + 0xAC = { 935, 3}, + 0xAD = { 938, 3}, + 0xAE = { 941, 14}, + 0xAF = { 955, 3}, + 0xB0 = { 958, 1}, + 0xB1 = { 959, 3}, + 0xB3 = { 962, 3}, + 0xB6 = { 965, 3}, + 0xB7 = { 968, 2}, + 0xB9 = { 970, 1}, + 0xBA = { 971, 12}, + 0xBB = { 983, 3}, + 0xBC = { 986, 3}, + 0xBD = { 989, 3}, + 0xBE = { 992, 3}, + 0xBF = { 995, 2}, + 0xC0 = { 997, 1}, + 0xC1 = { 998, 3}, + 0xC2 = {1001, 1}, + 0xC6 = {1002, 1}, + 0xC7 = {1003, 16}, + 0xC8 = {1019, 2}, + 0xFF = {1021, 1}, }, { // prefix = 66 - 0x10 = {1010, 1}, - 0x11 = {1011, 1}, - 0x12 = {1012, 1}, - 0x13 = {1013, 1}, - 0x14 = {1014, 1}, - 0x15 = {1015, 1}, - 0x16 = {1016, 1}, - 0x17 = {1017, 1}, - 0x28 = {1018, 1}, - 0x29 = {1019, 1}, - 0x2B = {1020, 1}, - 0x2E = {1021, 1}, - 0x2F = {1022, 1}, - 0x50 = {1023, 2}, - 0x51 = {1025, 1}, - 0x54 = {1026, 1}, - 0x55 = {1027, 1}, - 0x56 = {1028, 1}, - 0x57 = {1029, 1}, - 0x58 = {1030, 1}, - 0x59 = {1031, 1}, - 0x5A = {1032, 1}, - 0x5B = {1033, 1}, - 0x5C = {1034, 1}, - 0x5D = {1035, 1}, - 0x5E = {1036, 1}, - 0x5F = {1037, 1}, - 0x60 = {1038, 1}, - 0x61 = {1039, 1}, - 0x62 = {1040, 1}, - 0x63 = {1041, 1}, - 0x64 = {1042, 1}, - 0x65 = {1043, 1}, - 0x66 = {1044, 1}, - 0x67 = {1045, 1}, - 0x68 = {1046, 1}, - 0x69 = {1047, 1}, - 0x6A = {1048, 1}, - 0x6B = {1049, 1}, - 0x6C = {1050, 1}, - 0x6D = {1051, 1}, - 0x6E = {1052, 2}, - 0x6F = {1054, 1}, - 0x70 = {1055, 1}, - 0x71 = {1056, 3}, - 0x72 = {1059, 3}, - 0x73 = {1062, 2}, - 0x74 = {1064, 1}, - 0x75 = {1065, 1}, - 0x76 = {1066, 1}, - 0x7C = {1067, 1}, - 0x7D = {1068, 1}, - 0x7E = {1069, 2}, - 0x7F = {1071, 1}, - 0xAE = {1072, 3}, - 0xC2 = {1075, 1}, - 0xC4 = {1076, 2}, - 0xC5 = {1078, 2}, - 0xC6 = {1080, 1}, - 0xC7 = {1081, 1}, - 0xD0 = {1082, 1}, - 0xD1 = {1083, 1}, - 0xD2 = {1084, 1}, - 0xD3 = {1085, 1}, - 0xD4 = {1086, 1}, - 0xD5 = {1087, 1}, - 0xD6 = {1088, 1}, - 0xD7 = {1089, 2}, - 0xD8 = {1091, 1}, - 0xD9 = {1092, 1}, - 0xDA = {1093, 1}, - 0xDB = {1094, 1}, - 0xDC = {1095, 1}, - 0xDD = {1096, 1}, - 0xDE = {1097, 1}, - 0xDF = {1098, 1}, - 0xE0 = {1099, 1}, - 0xE1 = {1100, 1}, - 0xE2 = {1101, 1}, - 0xE3 = {1102, 1}, - 0xE4 = {1103, 1}, - 0xE5 = {1104, 1}, - 0xE6 = {1105, 1}, - 0xE7 = {1106, 1}, - 0xE8 = {1107, 1}, - 0xE9 = {1108, 1}, - 0xEA = {1109, 1}, - 0xEB = {1110, 1}, - 0xEC = {1111, 1}, - 0xED = {1112, 1}, - 0xEE = {1113, 1}, - 0xEF = {1114, 1}, - 0xF1 = {1115, 1}, - 0xF2 = {1116, 1}, - 0xF3 = {1117, 1}, - 0xF4 = {1118, 1}, - 0xF5 = {1119, 1}, - 0xF6 = {1120, 1}, - 0xF7 = {1121, 1}, - 0xF8 = {1122, 1}, - 0xF9 = {1123, 1}, - 0xFA = {1124, 1}, - 0xFB = {1125, 1}, - 0xFC = {1126, 1}, - 0xFD = {1127, 1}, - 0xFE = {1128, 1}, + 0x10 = {1022, 1}, + 0x11 = {1023, 1}, + 0x12 = {1024, 1}, + 0x13 = {1025, 1}, + 0x14 = {1026, 1}, + 0x15 = {1027, 1}, + 0x16 = {1028, 1}, + 0x17 = {1029, 1}, + 0x28 = {1030, 1}, + 0x29 = {1031, 1}, + 0x2B = {1032, 1}, + 0x2E = {1033, 1}, + 0x2F = {1034, 1}, + 0x50 = {1035, 2}, + 0x51 = {1037, 1}, + 0x54 = {1038, 1}, + 0x55 = {1039, 1}, + 0x56 = {1040, 1}, + 0x57 = {1041, 1}, + 0x58 = {1042, 1}, + 0x59 = {1043, 1}, + 0x5A = {1044, 1}, + 0x5B = {1045, 1}, + 0x5C = {1046, 1}, + 0x5D = {1047, 1}, + 0x5E = {1048, 1}, + 0x5F = {1049, 1}, + 0x60 = {1050, 1}, + 0x61 = {1051, 1}, + 0x62 = {1052, 1}, + 0x63 = {1053, 1}, + 0x64 = {1054, 1}, + 0x65 = {1055, 1}, + 0x66 = {1056, 1}, + 0x67 = {1057, 1}, + 0x68 = {1058, 1}, + 0x69 = {1059, 1}, + 0x6A = {1060, 1}, + 0x6B = {1061, 1}, + 0x6C = {1062, 1}, + 0x6D = {1063, 1}, + 0x6E = {1064, 2}, + 0x6F = {1066, 1}, + 0x70 = {1067, 1}, + 0x71 = {1068, 3}, + 0x72 = {1071, 3}, + 0x73 = {1074, 2}, + 0x74 = {1076, 1}, + 0x75 = {1077, 1}, + 0x76 = {1078, 1}, + 0x7C = {1079, 1}, + 0x7D = {1080, 1}, + 0x7E = {1081, 2}, + 0x7F = {1083, 1}, + 0xAE = {1084, 3}, + 0xC2 = {1087, 1}, + 0xC4 = {1088, 2}, + 0xC5 = {1090, 2}, + 0xC6 = {1092, 1}, + 0xC7 = {1093, 1}, + 0xD0 = {1094, 1}, + 0xD1 = {1095, 1}, + 0xD2 = {1096, 1}, + 0xD3 = {1097, 1}, + 0xD4 = {1098, 1}, + 0xD5 = {1099, 1}, + 0xD6 = {1100, 1}, + 0xD7 = {1101, 2}, + 0xD8 = {1103, 1}, + 0xD9 = {1104, 1}, + 0xDA = {1105, 1}, + 0xDB = {1106, 1}, + 0xDC = {1107, 1}, + 0xDD = {1108, 1}, + 0xDE = {1109, 1}, + 0xDF = {1110, 1}, + 0xE0 = {1111, 1}, + 0xE1 = {1112, 1}, + 0xE2 = {1113, 1}, + 0xE3 = {1114, 1}, + 0xE4 = {1115, 1}, + 0xE5 = {1116, 1}, + 0xE6 = {1117, 1}, + 0xE7 = {1118, 1}, + 0xE8 = {1119, 1}, + 0xE9 = {1120, 1}, + 0xEA = {1121, 1}, + 0xEB = {1122, 1}, + 0xEC = {1123, 1}, + 0xED = {1124, 1}, + 0xEE = {1125, 1}, + 0xEF = {1126, 1}, + 0xF1 = {1127, 1}, + 0xF2 = {1128, 1}, + 0xF3 = {1129, 1}, + 0xF4 = {1130, 1}, + 0xF5 = {1131, 1}, + 0xF6 = {1132, 1}, + 0xF7 = {1133, 1}, + 0xF8 = {1134, 1}, + 0xF9 = {1135, 1}, + 0xFA = {1136, 1}, + 0xFB = {1137, 1}, + 0xFC = {1138, 1}, + 0xFD = {1139, 1}, + 0xFE = {1140, 1}, }, { // prefix = F3 - 0x01 = {1129, 6}, - 0x09 = {1135, 1}, - 0x10 = {1136, 1}, - 0x11 = {1137, 1}, - 0x12 = {1138, 1}, - 0x16 = {1139, 1}, - 0x1E = {1140, 4}, - 0x2A = {1144, 2}, - 0x2C = {1146, 2}, - 0x2D = {1148, 2}, - 0x51 = {1150, 1}, - 0x52 = {1151, 1}, - 0x53 = {1152, 1}, - 0x58 = {1153, 1}, - 0x59 = {1154, 1}, - 0x5A = {1155, 1}, - 0x5B = {1156, 1}, - 0x5C = {1157, 1}, - 0x5D = {1158, 1}, - 0x5E = {1159, 1}, - 0x5F = {1160, 1}, - 0x6F = {1161, 1}, - 0x70 = {1162, 1}, - 0x7E = {1163, 1}, - 0x7F = {1164, 1}, - 0xAE = {1165, 14}, - 0xB8 = {1179, 3}, - 0xBC = {1182, 3}, - 0xBD = {1185, 3}, - 0xC2 = {1188, 1}, - 0xC7 = {1189, 2}, - 0xE6 = {1191, 1}, + 0x01 = {1141, 6}, + 0x09 = {1147, 1}, + 0x10 = {1148, 1}, + 0x11 = {1149, 1}, + 0x12 = {1150, 1}, + 0x16 = {1151, 1}, + 0x1E = {1152, 4}, + 0x2A = {1156, 2}, + 0x2C = {1158, 2}, + 0x2D = {1160, 2}, + 0x51 = {1162, 1}, + 0x52 = {1163, 1}, + 0x53 = {1164, 1}, + 0x58 = {1165, 1}, + 0x59 = {1166, 1}, + 0x5A = {1167, 1}, + 0x5B = {1168, 1}, + 0x5C = {1169, 1}, + 0x5D = {1170, 1}, + 0x5E = {1171, 1}, + 0x5F = {1172, 1}, + 0x6F = {1173, 1}, + 0x70 = {1174, 1}, + 0x7E = {1175, 1}, + 0x7F = {1176, 1}, + 0xAE = {1177, 14}, + 0xB8 = {1191, 3}, + 0xBC = {1194, 3}, + 0xBD = {1197, 3}, + 0xC2 = {1200, 1}, + 0xC7 = {1201, 2}, + 0xE6 = {1203, 1}, }, { // prefix = F2 - 0x01 = {1192, 2}, - 0x10 = {1194, 1}, - 0x11 = {1195, 1}, - 0x12 = {1196, 1}, - 0x2A = {1197, 2}, - 0x2C = {1199, 2}, - 0x2D = {1201, 2}, - 0x51 = {1203, 1}, - 0x58 = {1204, 1}, - 0x59 = {1205, 1}, - 0x5A = {1206, 1}, - 0x5C = {1207, 1}, - 0x5D = {1208, 1}, - 0x5E = {1209, 1}, - 0x5F = {1210, 1}, - 0x70 = {1211, 1}, - 0x7C = {1212, 1}, - 0x7D = {1213, 1}, - 0xAE = {1214, 1}, - 0xC2 = {1215, 1}, - 0xD0 = {1216, 1}, - 0xE6 = {1217, 1}, - 0xF0 = {1218, 1}, + 0x01 = {1204, 2}, + 0x10 = {1206, 1}, + 0x11 = {1207, 1}, + 0x12 = {1208, 1}, + 0x2A = {1209, 2}, + 0x2C = {1211, 2}, + 0x2D = {1213, 2}, + 0x51 = {1215, 1}, + 0x58 = {1216, 1}, + 0x59 = {1217, 1}, + 0x5A = {1218, 1}, + 0x5C = {1219, 1}, + 0x5D = {1220, 1}, + 0x5E = {1221, 1}, + 0x5F = {1222, 1}, + 0x70 = {1223, 1}, + 0x7C = {1224, 1}, + 0x7D = {1225, 1}, + 0xAE = {1226, 1}, + 0xC2 = {1227, 1}, + 0xD0 = {1228, 1}, + 0xE6 = {1229, 1}, + 0xF0 = {1230, 1}, }, } @(rodata) DECODE_INDEX_ESC_0F38 := [4][256]lib.Decode_Index{ { // prefix = none - 0xC8 = {1219, 1}, - 0xC9 = {1220, 1}, - 0xCA = {1221, 1}, - 0xCB = {1222, 1}, - 0xCC = {1223, 1}, - 0xCD = {1224, 1}, - 0xF0 = {1225, 3}, - 0xF1 = {1228, 3}, - 0xF6 = {1231, 2}, - 0xF9 = {1233, 2}, - 0xFC = {1235, 2}, + 0xC8 = {1231, 1}, + 0xC9 = {1232, 1}, + 0xCA = {1233, 1}, + 0xCB = {1234, 1}, + 0xCC = {1235, 1}, + 0xCD = {1236, 1}, + 0xF0 = {1237, 3}, + 0xF1 = {1240, 3}, + 0xF6 = {1243, 2}, + 0xF9 = {1245, 2}, + 0xFC = {1247, 2}, }, { // prefix = 66 - 0x00 = {1237, 1}, - 0x01 = {1238, 1}, - 0x02 = {1239, 1}, - 0x03 = {1240, 1}, - 0x04 = {1241, 1}, - 0x05 = {1242, 1}, - 0x06 = {1243, 1}, - 0x07 = {1244, 1}, - 0x08 = {1245, 1}, - 0x09 = {1246, 1}, - 0x0A = {1247, 1}, - 0x0B = {1248, 1}, - 0x10 = {1249, 1}, - 0x14 = {1250, 1}, - 0x15 = {1251, 1}, - 0x17 = {1252, 1}, - 0x1C = {1253, 1}, - 0x1D = {1254, 1}, - 0x1E = {1255, 1}, - 0x20 = {1256, 1}, - 0x21 = {1257, 1}, - 0x22 = {1258, 1}, - 0x23 = {1259, 1}, - 0x24 = {1260, 1}, - 0x25 = {1261, 1}, - 0x28 = {1262, 1}, - 0x29 = {1263, 1}, - 0x2A = {1264, 1}, - 0x2B = {1265, 1}, - 0x30 = {1266, 1}, - 0x31 = {1267, 1}, - 0x32 = {1268, 1}, - 0x33 = {1269, 1}, - 0x34 = {1270, 1}, - 0x35 = {1271, 1}, - 0x37 = {1272, 1}, - 0x38 = {1273, 1}, - 0x39 = {1274, 1}, - 0x3A = {1275, 1}, - 0x3B = {1276, 1}, - 0x3C = {1277, 1}, - 0x3D = {1278, 1}, - 0x3E = {1279, 1}, - 0x3F = {1280, 1}, - 0x40 = {1281, 1}, - 0x41 = {1282, 1}, - 0x80 = {1283, 1}, - 0x81 = {1284, 1}, - 0x82 = {1285, 2}, - 0xDB = {1287, 1}, - 0xDC = {1288, 1}, - 0xDD = {1289, 1}, - 0xDE = {1290, 1}, - 0xDF = {1291, 1}, - 0xF5 = {1292, 2}, - 0xF6 = {1294, 2}, - 0xF8 = {1296, 1}, - 0xFC = {1297, 2}, + 0x00 = {1249, 1}, + 0x01 = {1250, 1}, + 0x02 = {1251, 1}, + 0x03 = {1252, 1}, + 0x04 = {1253, 1}, + 0x05 = {1254, 1}, + 0x06 = {1255, 1}, + 0x07 = {1256, 1}, + 0x08 = {1257, 1}, + 0x09 = {1258, 1}, + 0x0A = {1259, 1}, + 0x0B = {1260, 1}, + 0x10 = {1261, 1}, + 0x14 = {1262, 1}, + 0x15 = {1263, 1}, + 0x17 = {1264, 1}, + 0x1C = {1265, 1}, + 0x1D = {1266, 1}, + 0x1E = {1267, 1}, + 0x20 = {1268, 1}, + 0x21 = {1269, 1}, + 0x22 = {1270, 1}, + 0x23 = {1271, 1}, + 0x24 = {1272, 1}, + 0x25 = {1273, 1}, + 0x28 = {1274, 1}, + 0x29 = {1275, 1}, + 0x2A = {1276, 1}, + 0x2B = {1277, 1}, + 0x30 = {1278, 1}, + 0x31 = {1279, 1}, + 0x32 = {1280, 1}, + 0x33 = {1281, 1}, + 0x34 = {1282, 1}, + 0x35 = {1283, 1}, + 0x37 = {1284, 1}, + 0x38 = {1285, 1}, + 0x39 = {1286, 1}, + 0x3A = {1287, 1}, + 0x3B = {1288, 1}, + 0x3C = {1289, 1}, + 0x3D = {1290, 1}, + 0x3E = {1291, 1}, + 0x3F = {1292, 1}, + 0x40 = {1293, 1}, + 0x41 = {1294, 1}, + 0x80 = {1295, 1}, + 0x81 = {1296, 1}, + 0x82 = {1297, 2}, + 0xDB = {1299, 1}, + 0xDC = {1300, 1}, + 0xDD = {1301, 1}, + 0xDE = {1302, 1}, + 0xDF = {1303, 1}, + 0xF5 = {1304, 2}, + 0xF6 = {1306, 2}, + 0xF8 = {1308, 1}, + 0xFC = {1309, 2}, }, { // prefix = F3 - 0xF6 = {1299, 2}, - 0xF8 = {1301, 1}, - 0xFC = {1302, 2}, + 0xF6 = {1311, 2}, + 0xF8 = {1313, 1}, + 0xFC = {1314, 2}, }, { // prefix = F2 - 0xF0 = {1304, 2}, - 0xF1 = {1306, 3}, - 0xF8 = {1309, 1}, - 0xFC = {1310, 2}, + 0xF0 = {1316, 2}, + 0xF1 = {1318, 3}, + 0xF8 = {1321, 1}, + 0xFC = {1322, 2}, }, } @(rodata) DECODE_INDEX_ESC_0F3A := [4][256]lib.Decode_Index{ { // prefix = none - 0xCC = {1312, 1}, + 0xCC = {1324, 1}, }, { // prefix = 66 - 0x08 = {1313, 1}, - 0x09 = {1314, 1}, - 0x0A = {1315, 1}, - 0x0B = {1316, 1}, - 0x0C = {1317, 1}, - 0x0D = {1318, 1}, - 0x0E = {1319, 1}, - 0x0F = {1320, 1}, - 0x14 = {1321, 1}, - 0x16 = {1322, 2}, - 0x17 = {1324, 1}, - 0x20 = {1325, 1}, - 0x21 = {1326, 1}, - 0x22 = {1327, 2}, - 0x40 = {1329, 1}, - 0x41 = {1330, 1}, - 0x42 = {1331, 1}, - 0x44 = {1332, 1}, - 0x60 = {1333, 1}, - 0x61 = {1334, 1}, - 0x62 = {1335, 1}, - 0x63 = {1336, 1}, - 0xDF = {1337, 1}, + 0x08 = {1325, 1}, + 0x09 = {1326, 1}, + 0x0A = {1327, 1}, + 0x0B = {1328, 1}, + 0x0C = {1329, 1}, + 0x0D = {1330, 1}, + 0x0E = {1331, 1}, + 0x0F = {1332, 1}, + 0x14 = {1333, 1}, + 0x16 = {1334, 2}, + 0x17 = {1336, 1}, + 0x20 = {1337, 1}, + 0x21 = {1338, 1}, + 0x22 = {1339, 2}, + 0x40 = {1341, 1}, + 0x41 = {1342, 1}, + 0x42 = {1343, 1}, + 0x44 = {1344, 1}, + 0x60 = {1345, 1}, + 0x61 = {1346, 1}, + 0x62 = {1347, 1}, + 0x63 = {1348, 1}, + 0xDF = {1349, 1}, }, { // prefix = F3 }, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 08553ef83..3eb58e95a 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_x86_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2466]lib.Encoding{ +ENCODE_FORMS := [2478]lib.Encoding{ // .MOV {.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {explicit_count=2}}, {.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {explicit_count=2}}, @@ -360,6 +360,19 @@ ENCODE_FORMS := [2466]lib.Encoding{ {.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, + // .SAL + {.SAL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true, explicit_count=2}}, + {.SAL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}}, + {.SAL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}}, + {.SAL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .ROL {.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, @@ -3718,7 +3731,7 @@ ENCODE_FORMS := [2466]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2466]lib.Clobber{ +CLOBBER_FORMS := [2478]lib.Clobber{ // .MOV {written={0}, read={1}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, @@ -4070,6 +4083,19 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .SAL + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .ROL {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, @@ -7459,1221 +7485,1222 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .SHL = { 286, 12}, .SHR = { 298, 12}, .SAR = { 310, 12}, - .ROL = { 322, 12}, - .ROR = { 334, 12}, - .RCL = { 346, 12}, - .RCR = { 358, 12}, - .SHLD = { 370, 6}, - .SHRD = { 376, 6}, - .BT = { 382, 6}, - .BTS = { 388, 6}, - .BTR = { 394, 6}, - .BTC = { 400, 6}, - .BSF = { 406, 3}, - .BSR = { 409, 3}, - .POPCNT = { 412, 3}, - .LZCNT = { 415, 3}, - .TZCNT = { 418, 3}, - .JMP = { 421, 6}, - .JA = { 427, 2}, - .JAE = { 429, 2}, - .JB = { 431, 2}, - .JBE = { 433, 2}, - .JC = { 435, 2}, - .JE = { 437, 2}, - .JZ = { 439, 2}, - .JG = { 441, 2}, - .JGE = { 443, 2}, - .JL = { 445, 2}, - .JLE = { 447, 2}, - .JNA = { 449, 2}, - .JNAE = { 451, 2}, - .JNB = { 453, 2}, - .JNBE = { 455, 2}, - .JNC = { 457, 2}, - .JNE = { 459, 2}, - .JNZ = { 461, 2}, - .JNG = { 463, 2}, - .JNGE = { 465, 2}, - .JNL = { 467, 2}, - .JNLE = { 469, 2}, - .JNO = { 471, 2}, - .JNP = { 473, 2}, - .JNS = { 475, 2}, - .JO = { 477, 2}, - .JP = { 479, 2}, - .JPE = { 481, 2}, - .JPO = { 483, 2}, - .JS = { 485, 2}, - .JCXZ = { 487, 1}, - .JECXZ = { 488, 1}, - .JRCXZ = { 489, 1}, - .LOOP = { 490, 1}, - .LOOPE = { 491, 1}, - .LOOPNE = { 492, 1}, - .CALL = { 493, 5}, - .RET = { 498, 2}, - .IRET = { 500, 1}, - .IRETD = { 501, 1}, - .IRETQ = { 502, 1}, - .INT = { 503, 1}, - .INT3 = { 504, 1}, - .INTO = { 505, 1}, - .SYSCALL = { 506, 1}, - .SYSRET = { 507, 1}, - .SYSENTER = { 508, 1}, - .SYSEXIT = { 509, 1}, - .SETA = { 510, 1}, - .SETAE = { 511, 1}, - .SETB = { 512, 1}, - .SETBE = { 513, 1}, - .SETC = { 514, 1}, - .SETE = { 515, 1}, - .SETG = { 516, 1}, - .SETGE = { 517, 1}, - .SETL = { 518, 1}, - .SETLE = { 519, 1}, - .SETNA = { 520, 1}, - .SETNAE = { 521, 1}, - .SETNB = { 522, 1}, - .SETNBE = { 523, 1}, - .SETNC = { 524, 1}, - .SETNE = { 525, 1}, - .SETNG = { 526, 1}, - .SETNGE = { 527, 1}, - .SETNL = { 528, 1}, - .SETNLE = { 529, 1}, - .SETNO = { 530, 1}, - .SETNP = { 531, 1}, - .SETNS = { 532, 1}, - .SETNZ = { 533, 1}, - .SETO = { 534, 1}, - .SETP = { 535, 1}, - .SETPE = { 536, 1}, - .SETPO = { 537, 1}, - .SETS = { 538, 1}, - .SETZ = { 539, 1}, - .CMOVA = { 540, 3}, - .CMOVAE = { 543, 3}, - .CMOVB = { 546, 3}, - .CMOVBE = { 549, 3}, - .CMOVC = { 552, 3}, - .CMOVE = { 555, 3}, - .CMOVG = { 558, 3}, - .CMOVGE = { 561, 3}, - .CMOVL = { 564, 3}, - .CMOVLE = { 567, 3}, - .CMOVNA = { 570, 3}, - .CMOVNAE = { 573, 3}, - .CMOVNB = { 576, 3}, - .CMOVNBE = { 579, 3}, - .CMOVNC = { 582, 3}, - .CMOVNE = { 585, 3}, - .CMOVNG = { 588, 3}, - .CMOVNGE = { 591, 3}, - .CMOVNL = { 594, 3}, - .CMOVNLE = { 597, 3}, - .CMOVNO = { 600, 3}, - .CMOVNP = { 603, 3}, - .CMOVNS = { 606, 3}, - .CMOVNZ = { 609, 3}, - .CMOVO = { 612, 3}, - .CMOVP = { 615, 3}, - .CMOVPE = { 618, 3}, - .CMOVPO = { 621, 3}, - .CMOVS = { 624, 3}, - .CMOVZ = { 627, 3}, - .MOVS = { 630, 1}, - .MOVSB = { 631, 1}, - .MOVSW = { 632, 1}, - .MOVSD = { 633, 3}, - .MOVSQ = { 636, 1}, - .CMPS = { 637, 1}, - .CMPSB = { 638, 1}, - .CMPSW = { 639, 1}, - .CMPSD = { 640, 2}, - .CMPSQ = { 642, 1}, - .SCAS = { 643, 1}, - .SCASB = { 644, 1}, - .SCASW = { 645, 1}, - .SCASD = { 646, 1}, - .SCASQ = { 647, 1}, - .LODS = { 648, 1}, - .LODSB = { 649, 1}, - .LODSW = { 650, 1}, - .LODSD = { 651, 1}, - .LODSQ = { 652, 1}, - .STOS = { 653, 1}, - .STOSB = { 654, 1}, - .STOSW = { 655, 1}, - .STOSD = { 656, 1}, - .STOSQ = { 657, 1}, - .CLC = { 658, 1}, - .STC = { 659, 1}, - .CMC = { 660, 1}, - .CLD = { 661, 1}, - .STD = { 662, 1}, - .CLI = { 663, 1}, - .STI = { 664, 1}, - .LAHF = { 665, 1}, - .SAHF = { 666, 1}, - .PUSHF = { 667, 1}, - .PUSHFD = { 668, 1}, - .PUSHFQ = { 669, 1}, - .POPF = { 670, 1}, - .POPFD = { 671, 1}, - .POPFQ = { 672, 1}, - .NOP = { 673, 4}, - .HLT = { 677, 1}, - .WAIT = { 678, 1}, - .LOCK = { 679, 1}, - .UD0 = { 680, 1}, - .UD1 = { 681, 1}, - .UD2 = { 682, 1}, - .CPUID = { 683, 1}, - .RDTSC = { 684, 1}, - .RDTSCP = { 685, 1}, - .RDPMC = { 686, 1}, - .XGETBV = { 687, 1}, - .XSETBV = { 688, 1}, - .CBW = { 689, 1}, - .CWDE = { 690, 1}, - .CDQE = { 691, 1}, - .CWD = { 692, 1}, - .CDQ = { 693, 1}, - .CQO = { 694, 1}, - .ANDN = { 695, 2}, - .BEXTR = { 697, 2}, - .BLSI = { 699, 2}, - .BLSMSK = { 701, 2}, - .BLSR = { 703, 2}, - .BZHI = { 705, 2}, - .PDEP = { 707, 2}, - .PEXT = { 709, 2}, - .RORX = { 711, 2}, - .SARX = { 713, 2}, - .SHLX = { 715, 2}, - .SHRX = { 717, 2}, - .MULX = { 719, 2}, - .ADCX = { 721, 2}, - .ADOX = { 723, 2}, - .MOVAPS = { 725, 2}, - .MOVUPS = { 727, 2}, - .MOVAPD = { 729, 2}, - .MOVUPD = { 731, 2}, - .MOVSS = { 733, 2}, - .MOVDQA = { 735, 2}, - .MOVDQU = { 737, 2}, - .MOVQ = { 739, 6}, - .MOVD = { 745, 4}, - .MOVLPS = { 749, 2}, - .MOVHPS = { 751, 2}, - .MOVLPD = { 753, 2}, - .MOVHPD = { 755, 2}, - .MOVLHPS = { 757, 1}, - .MOVHLPS = { 758, 1}, - .MOVMSKPS = { 759, 2}, - .MOVMSKPD = { 761, 2}, - .MOVNTPS = { 763, 1}, - .MOVNTPD = { 764, 1}, - .MOVNTDQ = { 765, 1}, - .MOVNTDQA = { 766, 1}, - .ADDPS = { 767, 1}, - .ADDPD = { 768, 1}, - .ADDSS = { 769, 1}, - .ADDSD = { 770, 1}, - .SUBPS = { 771, 1}, - .SUBPD = { 772, 1}, - .SUBSS = { 773, 1}, - .SUBSD = { 774, 1}, - .MULPS = { 775, 1}, - .MULPD = { 776, 1}, - .MULSS = { 777, 1}, - .MULSD = { 778, 1}, - .DIVPS = { 779, 1}, - .DIVPD = { 780, 1}, - .DIVSS = { 781, 1}, - .DIVSD = { 782, 1}, - .SQRTPS = { 783, 1}, - .SQRTPD = { 784, 1}, - .SQRTSS = { 785, 1}, - .SQRTSD = { 786, 1}, - .RCPPS = { 787, 1}, - .RCPSS = { 788, 1}, - .RSQRTPS = { 789, 1}, - .RSQRTSS = { 790, 1}, - .MAXPS = { 791, 1}, - .MAXPD = { 792, 1}, - .MAXSS = { 793, 1}, - .MAXSD = { 794, 1}, - .MINPS = { 795, 1}, - .MINPD = { 796, 1}, - .MINSS = { 797, 1}, - .MINSD = { 798, 1}, - .ANDPS = { 799, 1}, - .ANDPD = { 800, 1}, - .ANDNPS = { 801, 1}, - .ANDNPD = { 802, 1}, - .ORPS = { 803, 1}, - .ORPD = { 804, 1}, - .XORPS = { 805, 1}, - .XORPD = { 806, 1}, - .CMPPS = { 807, 1}, - .CMPPD = { 808, 1}, - .CMPSS = { 809, 1}, - .COMISS = { 810, 1}, - .COMISD = { 811, 1}, - .UCOMISS = { 812, 1}, - .UCOMISD = { 813, 1}, - .SHUFPS = { 814, 1}, - .SHUFPD = { 815, 1}, - .UNPCKLPS = { 816, 1}, - .UNPCKHPS = { 817, 1}, - .UNPCKLPD = { 818, 1}, - .UNPCKHPD = { 819, 1}, - .CVTPS2PD = { 820, 1}, - .CVTPD2PS = { 821, 1}, - .CVTSS2SD = { 822, 1}, - .CVTSD2SS = { 823, 1}, - .CVTPS2DQ = { 824, 1}, - .CVTPD2DQ = { 825, 1}, - .CVTDQ2PS = { 826, 1}, - .CVTDQ2PD = { 827, 1}, - .CVTSS2SI = { 828, 2}, - .CVTSD2SI = { 830, 2}, - .CVTSI2SS = { 832, 2}, - .CVTSI2SD = { 834, 2}, - .CVTTPS2DQ = { 836, 1}, - .CVTTPD2DQ = { 837, 1}, - .CVTTSS2SI = { 838, 2}, - .CVTTSD2SI = { 840, 2}, - .PADDB = { 842, 1}, - .PADDW = { 843, 1}, - .PADDD = { 844, 1}, - .PADDQ = { 845, 1}, - .PSUBB = { 846, 1}, - .PSUBW = { 847, 1}, - .PSUBD = { 848, 1}, - .PSUBQ = { 849, 1}, - .PADDSB = { 850, 1}, - .PADDSW = { 851, 1}, - .PADDUSB = { 852, 1}, - .PADDUSW = { 853, 1}, - .PSUBSB = { 854, 1}, - .PSUBSW = { 855, 1}, - .PSUBUSB = { 856, 1}, - .PSUBUSW = { 857, 1}, - .PMULLW = { 858, 1}, - .PMULHW = { 859, 1}, - .PMULHUW = { 860, 1}, - .PMULUDQ = { 861, 1}, - .PMADDWD = { 862, 1}, - .PAND = { 863, 1}, - .PANDN = { 864, 1}, - .POR = { 865, 1}, - .PXOR = { 866, 1}, - .PSLLW = { 867, 2}, - .PSLLD = { 869, 2}, - .PSLLQ = { 871, 2}, - .PSRLW = { 873, 2}, - .PSRLD = { 875, 2}, - .PSRLQ = { 877, 2}, - .PSRAW = { 879, 2}, - .PSRAD = { 881, 2}, - .PCMPEQB = { 883, 1}, - .PCMPEQW = { 884, 1}, - .PCMPEQD = { 885, 1}, - .PCMPGTB = { 886, 1}, - .PCMPGTW = { 887, 1}, - .PCMPGTD = { 888, 1}, - .PACKSSWB = { 889, 1}, - .PACKSSDW = { 890, 1}, - .PACKUSWB = { 891, 1}, - .PUNPCKLBW = { 892, 1}, - .PUNPCKLWD = { 893, 1}, - .PUNPCKLDQ = { 894, 1}, - .PUNPCKLQDQ = { 895, 1}, - .PUNPCKHBW = { 896, 1}, - .PUNPCKHWD = { 897, 1}, - .PUNPCKHDQ = { 898, 1}, - .PUNPCKHQDQ = { 899, 1}, - .PSHUFD = { 900, 1}, - .PSHUFHW = { 901, 1}, - .PSHUFLW = { 902, 1}, - .PSHUFW = { 903, 1}, - .PEXTRW = { 904, 2}, - .PINSRW = { 906, 2}, - .PMOVMSKB = { 908, 2}, - .PAVGB = { 910, 1}, - .PAVGW = { 911, 1}, - .PMAXUB = { 912, 1}, - .PMAXSW = { 913, 1}, - .PMINUB = { 914, 1}, - .PMINSW = { 915, 1}, - .PSADBW = { 916, 1}, - .MASKMOVDQU = { 917, 1}, - .LFENCE = { 918, 1}, - .SFENCE = { 919, 1}, - .MFENCE = { 920, 1}, - .PAUSE = { 921, 1}, - .CLFLUSH = { 922, 1}, - .ADDSUBPS = { 923, 1}, - .ADDSUBPD = { 924, 1}, - .HADDPS = { 925, 1}, - .HADDPD = { 926, 1}, - .HSUBPS = { 927, 1}, - .HSUBPD = { 928, 1}, - .MOVDDUP = { 929, 1}, - .MOVSLDUP = { 930, 1}, - .MOVSHDUP = { 931, 1}, - .LDDQU = { 932, 1}, - .PSHUFB = { 933, 1}, - .PHADDW = { 934, 1}, - .PHADDD = { 935, 1}, - .PHADDSW = { 936, 1}, - .PHSUBW = { 937, 1}, - .PHSUBD = { 938, 1}, - .PHSUBSW = { 939, 1}, - .PMADDUBSW = { 940, 1}, - .PMULHRSW = { 941, 1}, - .PSIGNB = { 942, 1}, - .PSIGNW = { 943, 1}, - .PSIGND = { 944, 1}, - .PABSB = { 945, 1}, - .PABSW = { 946, 1}, - .PABSD = { 947, 1}, - .PALIGNR = { 948, 1}, - .BLENDPS = { 949, 1}, - .BLENDPD = { 950, 1}, - .BLENDVPS = { 951, 1}, - .BLENDVPD = { 952, 1}, - .PBLENDW = { 953, 1}, - .PBLENDVB = { 954, 1}, - .DPPS = { 955, 1}, - .DPPD = { 956, 1}, - .EXTRACTPS = { 957, 1}, - .INSERTPS = { 958, 1}, - .MPSADBW = { 959, 1}, - .PACKUSDW = { 960, 1}, - .PEXTRB = { 961, 1}, - .PEXTRD = { 962, 1}, - .PEXTRQ = { 963, 1}, - .PHMINPOSUW = { 964, 1}, - .PINSRB = { 965, 1}, - .PINSRD = { 966, 1}, - .PINSRQ = { 967, 1}, - .PMAXSB = { 968, 1}, - .PMAXSD = { 969, 1}, - .PMAXUW = { 970, 1}, - .PMAXUD = { 971, 1}, - .PMINSB = { 972, 1}, - .PMINSD = { 973, 1}, - .PMINUW = { 974, 1}, - .PMINUD = { 975, 1}, - .PMOVSXBW = { 976, 1}, - .PMOVSXBD = { 977, 1}, - .PMOVSXBQ = { 978, 1}, - .PMOVSXWD = { 979, 1}, - .PMOVSXWQ = { 980, 1}, - .PMOVSXDQ = { 981, 1}, - .PMOVZXBW = { 982, 1}, - .PMOVZXBD = { 983, 1}, - .PMOVZXBQ = { 984, 1}, - .PMOVZXWD = { 985, 1}, - .PMOVZXWQ = { 986, 1}, - .PMOVZXDQ = { 987, 1}, - .PMULDQ = { 988, 1}, - .PMULLD = { 989, 1}, - .PTEST = { 990, 1}, - .ROUNDPS = { 991, 1}, - .ROUNDPD = { 992, 1}, - .ROUNDSS = { 993, 1}, - .ROUNDSD = { 994, 1}, - .PCMPEQQ = { 995, 1}, - .CRC32 = { 996, 5}, - .PCMPESTRI = { 1001, 1}, - .PCMPESTRM = { 1002, 1}, - .PCMPISTRI = { 1003, 1}, - .PCMPISTRM = { 1004, 1}, - .PCMPGTQ = { 1005, 1}, - .PCLMULQDQ = { 1006, 1}, - .AESDEC = { 1007, 1}, - .AESDECLAST = { 1008, 1}, - .AESENC = { 1009, 1}, - .AESENCLAST = { 1010, 1}, - .AESIMC = { 1011, 1}, - .AESKEYGENASSIST = { 1012, 1}, - .SHA1MSG1 = { 1013, 1}, - .SHA1MSG2 = { 1014, 1}, - .SHA1NEXTE = { 1015, 1}, - .SHA1RNDS4 = { 1016, 1}, - .SHA256MSG1 = { 1017, 1}, - .SHA256MSG2 = { 1018, 1}, - .SHA256RNDS2 = { 1019, 1}, - .VADDPS = { 1020, 2}, - .VADDPD = { 1022, 2}, - .VADDSS = { 1024, 1}, - .VADDSD = { 1025, 1}, - .VSUBPS = { 1026, 2}, - .VSUBPD = { 1028, 2}, - .VSUBSS = { 1030, 1}, - .VSUBSD = { 1031, 1}, - .VMULPS = { 1032, 2}, - .VMULPD = { 1034, 2}, - .VMULSS = { 1036, 1}, - .VMULSD = { 1037, 1}, - .VDIVPS = { 1038, 2}, - .VDIVPD = { 1040, 2}, - .VDIVSS = { 1042, 1}, - .VDIVSD = { 1043, 1}, - .VSQRTPS = { 1044, 2}, - .VSQRTPD = { 1046, 2}, - .VSQRTSS = { 1048, 1}, - .VSQRTSD = { 1049, 1}, - .VRCPPS = { 1050, 2}, - .VRCPSS = { 1052, 1}, - .VRSQRTPS = { 1053, 2}, - .VRSQRTSS = { 1055, 1}, - .VMAXPS = { 1056, 2}, - .VMAXPD = { 1058, 2}, - .VMAXSS = { 1060, 1}, - .VMAXSD = { 1061, 1}, - .VMINPS = { 1062, 2}, - .VMINPD = { 1064, 2}, - .VMINSS = { 1066, 1}, - .VMINSD = { 1067, 1}, - .VANDPS = { 1068, 2}, - .VANDPD = { 1070, 2}, - .VANDNPS = { 1072, 2}, - .VANDNPD = { 1074, 2}, - .VORPS = { 1076, 2}, - .VORPD = { 1078, 2}, - .VXORPS = { 1080, 2}, - .VXORPD = { 1082, 2}, - .VCMPPS = { 1084, 2}, - .VCMPPD = { 1086, 2}, - .VCMPSS = { 1088, 1}, - .VCMPSD = { 1089, 1}, - .VCOMISS = { 1090, 1}, - .VCOMISD = { 1091, 1}, - .VUCOMISS = { 1092, 1}, - .VUCOMISD = { 1093, 1}, - .VSHUFPS = { 1094, 2}, - .VSHUFPD = { 1096, 2}, - .VUNPCKLPS = { 1098, 2}, - .VUNPCKHPS = { 1100, 2}, - .VUNPCKLPD = { 1102, 2}, - .VUNPCKHPD = { 1104, 2}, - .VBLENDPS = { 1106, 2}, - .VBLENDPD = { 1108, 2}, - .VBLENDVPS = { 1110, 2}, - .VBLENDVPD = { 1112, 2}, - .VDPPS = { 1114, 2}, - .VDPPD = { 1116, 1}, - .VROUNDPS = { 1117, 2}, - .VROUNDPD = { 1119, 2}, - .VROUNDSS = { 1121, 1}, - .VROUNDSD = { 1122, 1}, - .VEXTRACTPS = { 1123, 1}, - .VINSERTPS = { 1124, 1}, - .VMOVAPS = { 1125, 4}, - .VMOVUPS = { 1129, 4}, - .VMOVAPD = { 1133, 4}, - .VMOVUPD = { 1137, 4}, - .VMOVSS = { 1141, 3}, - .VMOVSD = { 1144, 3}, - .VMOVDQA = { 1147, 4}, - .VMOVDQU = { 1151, 4}, - .VMOVQ = { 1155, 4}, - .VMOVD = { 1159, 2}, - .VMOVLPS = { 1161, 2}, - .VMOVHPS = { 1163, 2}, - .VMOVLPD = { 1165, 2}, - .VMOVHPD = { 1167, 2}, - .VMOVLHPS = { 1169, 1}, - .VMOVHLPS = { 1170, 1}, - .VMOVMSKPS = { 1171, 2}, - .VMOVMSKPD = { 1173, 2}, - .VMOVNTPS = { 1175, 2}, - .VMOVNTPD = { 1177, 2}, - .VMOVNTDQ = { 1179, 2}, - .VMOVNTDQA = { 1181, 2}, - .VADDSUBPS = { 1183, 2}, - .VADDSUBPD = { 1185, 2}, - .VHADDPS = { 1187, 2}, - .VHADDPD = { 1189, 2}, - .VHSUBPS = { 1191, 2}, - .VHSUBPD = { 1193, 2}, - .VLDDQU = { 1195, 2}, - .VMOVDDUP = { 1197, 2}, - .VMOVSLDUP = { 1199, 2}, - .VMOVSHDUP = { 1201, 2}, - .VPCMPESTRI = { 1203, 1}, - .VPCMPESTRM = { 1204, 1}, - .VPCMPISTRI = { 1205, 1}, - .VPCMPISTRM = { 1206, 1}, - .VPBROADCASTB = { 1207, 4}, - .VPBROADCASTW = { 1211, 4}, - .VPBROADCASTD = { 1215, 4}, - .VPBROADCASTQ = { 1219, 4}, - .VCVTPS2PD = { 1223, 2}, - .VCVTPD2PS = { 1225, 2}, - .VCVTSS2SD = { 1227, 1}, - .VCVTSD2SS = { 1228, 1}, - .VCVTPS2DQ = { 1229, 2}, - .VCVTPD2DQ = { 1231, 2}, - .VCVTDQ2PS = { 1233, 2}, - .VCVTDQ2PD = { 1235, 2}, - .VCVTSS2SI = { 1237, 2}, - .VCVTSD2SI = { 1239, 2}, - .VCVTSI2SS = { 1241, 2}, - .VCVTSI2SD = { 1243, 2}, - .VCVTTPS2DQ = { 1245, 2}, - .VCVTTPD2DQ = { 1247, 2}, - .VCVTTSS2SI = { 1249, 2}, - .VCVTTSD2SI = { 1251, 2}, - .VPADDB = { 1253, 2}, - .VPADDW = { 1255, 2}, - .VPADDD = { 1257, 2}, - .VPADDQ = { 1259, 2}, - .VPSUBB = { 1261, 2}, - .VPSUBW = { 1263, 2}, - .VPSUBD = { 1265, 2}, - .VPSUBQ = { 1267, 2}, - .VPMULLW = { 1269, 2}, - .VPMULHW = { 1271, 2}, - .VPMULHUW = { 1273, 2}, - .VPMULUDQ = { 1275, 2}, - .VPMADDWD = { 1277, 2}, - .VPAND = { 1279, 2}, - .VPANDN = { 1281, 2}, - .VPOR = { 1283, 2}, - .VPXOR = { 1285, 2}, - .VPSLLW = { 1287, 4}, - .VPSLLD = { 1291, 4}, - .VPSLLQ = { 1295, 4}, - .VPSRLW = { 1299, 4}, - .VPSRLD = { 1303, 4}, - .VPSRLQ = { 1307, 4}, - .VPSRAW = { 1311, 4}, - .VPSRAD = { 1315, 4}, - .VPCMPEQB = { 1319, 2}, - .VPCMPEQW = { 1321, 2}, - .VPCMPEQD = { 1323, 2}, - .VPCMPEQQ = { 1325, 2}, - .VPCMPGTB = { 1327, 2}, - .VPCMPGTW = { 1329, 2}, - .VPCMPGTD = { 1331, 2}, - .VPCMPGTQ = { 1333, 2}, - .VPACKSSWB = { 1335, 2}, - .VPACKSSDW = { 1337, 2}, - .VPACKUSWB = { 1339, 2}, - .VPACKUSDW = { 1341, 2}, - .VPUNPCKLBW = { 1343, 2}, - .VPUNPCKLWD = { 1345, 2}, - .VPUNPCKLDQ = { 1347, 2}, - .VPUNPCKLQDQ = { 1349, 2}, - .VPUNPCKHBW = { 1351, 2}, - .VPUNPCKHWD = { 1353, 2}, - .VPUNPCKHDQ = { 1355, 2}, - .VPUNPCKHQDQ = { 1357, 2}, - .VPSHUFD = { 1359, 2}, - .VPSHUFHW = { 1361, 2}, - .VPSHUFLW = { 1363, 2}, - .VPEXTRB = { 1365, 1}, - .VPEXTRW = { 1366, 2}, - .VPEXTRD = { 1368, 1}, - .VPEXTRQ = { 1369, 1}, - .VPINSRB = { 1370, 1}, - .VPINSRW = { 1371, 1}, - .VPINSRD = { 1372, 1}, - .VPINSRQ = { 1373, 1}, - .VPMOVMSKB = { 1374, 2}, - .VPTEST = { 1376, 2}, - .VPSHUFB = { 1378, 2}, - .VPHADDW = { 1380, 2}, - .VPHADDD = { 1382, 2}, - .VPHADDSW = { 1384, 2}, - .VPHSUBW = { 1386, 2}, - .VPHSUBD = { 1388, 2}, - .VPHSUBSW = { 1390, 2}, - .VPMADDUBSW = { 1392, 2}, - .VPMULHRSW = { 1394, 2}, - .VPSIGNB = { 1396, 2}, - .VPSIGNW = { 1398, 2}, - .VPSIGND = { 1400, 2}, - .VPABSB = { 1402, 2}, - .VPABSW = { 1404, 2}, - .VPABSD = { 1406, 2}, - .VPALIGNR = { 1408, 2}, - .VPBLENDW = { 1410, 2}, - .VPBLENDVB = { 1412, 2}, - .VMPSADBW = { 1414, 2}, - .VPHMINPOSUW = { 1416, 1}, - .VPMAXSB = { 1417, 2}, - .VPMAXSD = { 1419, 2}, - .VPMAXUW = { 1421, 2}, - .VPMAXUD = { 1423, 2}, - .VPMINSB = { 1425, 2}, - .VPMINSD = { 1427, 2}, - .VPMINUW = { 1429, 2}, - .VPMINUD = { 1431, 2}, - .VPMOVSXBW = { 1433, 2}, - .VPMOVSXBD = { 1435, 2}, - .VPMOVSXBQ = { 1437, 2}, - .VPMOVSXWD = { 1439, 2}, - .VPMOVSXWQ = { 1441, 2}, - .VPMOVSXDQ = { 1443, 2}, - .VPMOVZXBW = { 1445, 2}, - .VPMOVZXBD = { 1447, 2}, - .VPMOVZXBQ = { 1449, 2}, - .VPMOVZXWD = { 1451, 2}, - .VPMOVZXWQ = { 1453, 2}, - .VPMOVZXDQ = { 1455, 2}, - .VPMULDQ = { 1457, 2}, - .VPMULLD = { 1459, 2}, - .VMASKMOVDQU = { 1461, 1}, - .VPCLMULQDQ = { 1462, 2}, - .VAESDEC = { 1464, 1}, - .VAESDECLAST = { 1465, 1}, - .VAESENC = { 1466, 1}, - .VAESENCLAST = { 1467, 1}, - .VAESIMC = { 1468, 1}, - .VAESKEYGENASSIST = { 1469, 1}, - .VBROADCASTSS = { 1470, 4}, - .VBROADCASTSD = { 1474, 2}, - .VBROADCASTF128 = { 1476, 1}, - .VEXTRACTF128 = { 1477, 1}, - .VINSERTF128 = { 1478, 1}, - .VPERM2F128 = { 1479, 1}, - .VMASKMOVPS = { 1480, 4}, - .VMASKMOVPD = { 1484, 4}, - .VTESTPS = { 1488, 2}, - .VTESTPD = { 1490, 2}, - .VZEROALL = { 1492, 1}, - .VZEROUPPER = { 1493, 1}, - .VBROADCASTI128 = { 1494, 1}, - .VEXTRACTI128 = { 1495, 1}, - .VINSERTI128 = { 1496, 1}, - .VPERM2I128 = { 1497, 1}, - .VPERMD = { 1498, 1}, - .VPERMPS = { 1499, 1}, - .VPERMQ = { 1500, 1}, - .VPERMPD = { 1501, 1}, - .VPBLENDD = { 1502, 2}, - .VPSLLVD = { 1504, 2}, - .VPSLLVQ = { 1506, 2}, - .VPSRLVD = { 1508, 2}, - .VPSRLVQ = { 1510, 2}, - .VPSRAVD = { 1512, 2}, - .VPMASKMOVD = { 1514, 4}, - .VPMASKMOVQ = { 1518, 4}, - .VGATHERDPS = { 1522, 2}, - .VGATHERDPD = { 1524, 2}, - .VGATHERQPS = { 1526, 2}, - .VGATHERQPD = { 1528, 2}, - .VPGATHERDD = { 1530, 2}, - .VPGATHERDQ = { 1532, 2}, - .VPGATHERQD = { 1534, 2}, - .VPGATHERQQ = { 1536, 2}, - .VFMADD132PS = { 1538, 2}, - .VFMADD213PS = { 1540, 2}, - .VFMADD231PS = { 1542, 2}, - .VFMADD132PD = { 1544, 2}, - .VFMADD213PD = { 1546, 2}, - .VFMADD231PD = { 1548, 2}, - .VFMADD132SS = { 1550, 1}, - .VFMADD213SS = { 1551, 1}, - .VFMADD231SS = { 1552, 1}, - .VFMADD132SD = { 1553, 1}, - .VFMADD213SD = { 1554, 1}, - .VFMADD231SD = { 1555, 1}, - .VFMSUB132PS = { 1556, 2}, - .VFMSUB213PS = { 1558, 2}, - .VFMSUB231PS = { 1560, 2}, - .VFMSUB132PD = { 1562, 2}, - .VFMSUB213PD = { 1564, 2}, - .VFMSUB231PD = { 1566, 2}, - .VFMSUB132SS = { 1568, 1}, - .VFMSUB213SS = { 1569, 1}, - .VFMSUB231SS = { 1570, 1}, - .VFMSUB132SD = { 1571, 1}, - .VFMSUB213SD = { 1572, 1}, - .VFMSUB231SD = { 1573, 1}, - .VFNMADD132PS = { 1574, 2}, - .VFNMADD213PS = { 1576, 2}, - .VFNMADD231PS = { 1578, 2}, - .VFNMADD132PD = { 1580, 2}, - .VFNMADD213PD = { 1582, 2}, - .VFNMADD231PD = { 1584, 2}, - .VFNMADD132SS = { 1586, 1}, - .VFNMADD213SS = { 1587, 1}, - .VFNMADD231SS = { 1588, 1}, - .VFNMADD132SD = { 1589, 1}, - .VFNMADD213SD = { 1590, 1}, - .VFNMADD231SD = { 1591, 1}, - .VFNMSUB132PS = { 1592, 2}, - .VFNMSUB213PS = { 1594, 2}, - .VFNMSUB231PS = { 1596, 2}, - .VFNMSUB132PD = { 1598, 2}, - .VFNMSUB213PD = { 1600, 2}, - .VFNMSUB231PD = { 1602, 2}, - .VFNMSUB132SS = { 1604, 1}, - .VFNMSUB213SS = { 1605, 1}, - .VFNMSUB231SS = { 1606, 1}, - .VFNMSUB132SD = { 1607, 1}, - .VFNMSUB213SD = { 1608, 1}, - .VFNMSUB231SD = { 1609, 1}, - .VFMADDSUB132PS = { 1610, 2}, - .VFMADDSUB213PS = { 1612, 2}, - .VFMADDSUB231PS = { 1614, 2}, - .VFMADDSUB132PD = { 1616, 2}, - .VFMADDSUB213PD = { 1618, 2}, - .VFMADDSUB231PD = { 1620, 2}, - .VFMSUBADD132PS = { 1622, 2}, - .VFMSUBADD213PS = { 1624, 2}, - .VFMSUBADD231PS = { 1626, 2}, - .VFMSUBADD132PD = { 1628, 2}, - .VFMSUBADD213PD = { 1630, 2}, - .VFMSUBADD231PD = { 1632, 2}, - .VCVTPH2PS = { 1634, 3}, - .VCVTPS2PH = { 1637, 3}, - .VMOVDQA32 = { 1640, 6}, - .VMOVDQA64 = { 1646, 6}, - .VMOVDQU8 = { 1652, 6}, - .VMOVDQU16 = { 1658, 6}, - .VMOVDQU32 = { 1664, 6}, - .VMOVDQU64 = { 1670, 6}, - .VPBLENDMB = { 1676, 3}, - .VPBLENDMW = { 1679, 3}, - .VPBLENDMD = { 1682, 3}, - .VPBLENDMQ = { 1685, 3}, - .VBLENDMPS = { 1688, 3}, - .VBLENDMPD = { 1691, 3}, - .VPCMPB = { 1694, 3}, - .VPCMPUB = { 1697, 3}, - .VPCMPW = { 1700, 3}, - .VPCMPUW = { 1703, 3}, - .VPCMPD = { 1706, 3}, - .VPCMPUD = { 1709, 3}, - .VPCMPQ = { 1712, 3}, - .VPCMPUQ = { 1715, 3}, - .VPTESTMB = { 1718, 3}, - .VPTESTMW = { 1721, 3}, - .VPTESTMD = { 1724, 3}, - .VPTESTMQ = { 1727, 3}, - .VPTESTNMB = { 1730, 3}, - .VPTESTNMW = { 1733, 3}, - .VPTESTNMD = { 1736, 3}, - .VPTESTNMQ = { 1739, 3}, - .VPCOMPRESSD = { 1742, 3}, - .VPCOMPRESSQ = { 1745, 3}, - .VCOMPRESSPS = { 1748, 3}, - .VCOMPRESSPD = { 1751, 3}, - .VPEXPANDD = { 1754, 3}, - .VPEXPANDQ = { 1757, 3}, - .VEXPANDPS = { 1760, 3}, - .VEXPANDPD = { 1763, 3}, - .VPCONFLICTD = { 1766, 3}, - .VPCONFLICTQ = { 1769, 3}, - .VPLZCNTD = { 1772, 3}, - .VPLZCNTQ = { 1775, 3}, - .VPERMI2B = { 1778, 3}, - .VPERMI2W = { 1781, 3}, - .VPERMI2D = { 1784, 3}, - .VPERMI2Q = { 1787, 3}, - .VPERMI2PS = { 1790, 3}, - .VPERMI2PD = { 1793, 3}, - .VPERMT2B = { 1796, 3}, - .VPERMT2W = { 1799, 3}, - .VPERMT2D = { 1802, 3}, - .VPERMT2Q = { 1805, 3}, - .VPERMT2PS = { 1808, 3}, - .VPERMT2PD = { 1811, 3}, - .VPERMB = { 1814, 3}, - .VPERMW = { 1817, 3}, - .VPMOVB2M = { 1820, 3}, - .VPMOVW2M = { 1823, 3}, - .VPMOVD2M = { 1826, 3}, - .VPMOVQ2M = { 1829, 3}, - .VPMOVM2B = { 1832, 3}, - .VPMOVM2W = { 1835, 3}, - .VPMOVM2D = { 1838, 3}, - .VPMOVM2Q = { 1841, 3}, - .VPMOVQB = { 1844, 3}, - .VPMOVSQB = { 1847, 3}, - .VPMOVUSQB = { 1850, 3}, - .VPMOVQW = { 1853, 3}, - .VPMOVSQW = { 1856, 3}, - .VPMOVUSQW = { 1859, 3}, - .VPMOVQD = { 1862, 3}, - .VPMOVSQD = { 1865, 3}, - .VPMOVUSQD = { 1868, 3}, - .VPMOVDB = { 1871, 3}, - .VPMOVSDB = { 1874, 3}, - .VPMOVUSDB = { 1877, 3}, - .VPMOVDW = { 1880, 3}, - .VPMOVSDW = { 1883, 3}, - .VPMOVUSDW = { 1886, 3}, - .VPMOVWB = { 1889, 3}, - .VPMOVSWB = { 1892, 3}, - .VPMOVUSWB = { 1895, 3}, - .VPROLD = { 1898, 3}, - .VPROLQ = { 1901, 3}, - .VPROLVD = { 1904, 3}, - .VPROLVQ = { 1907, 3}, - .VPRORD = { 1910, 3}, - .VPRORQ = { 1913, 3}, - .VPRORVD = { 1916, 3}, - .VPRORVQ = { 1919, 3}, - .VPSCATTERDD = { 1922, 3}, - .VPSCATTERDQ = { 1925, 3}, - .VPSCATTERQD = { 1928, 3}, - .VPSCATTERQQ = { 1931, 3}, - .VSCATTERDPS = { 1934, 3}, - .VSCATTERDPD = { 1937, 3}, - .VSCATTERQPS = { 1940, 3}, - .VSCATTERQPD = { 1943, 3}, - .VPSRAVQ = { 1946, 3}, - .VPSRAVW = { 1949, 3}, - .VPSLLVW = { 1952, 3}, - .VPSRLVW = { 1955, 3}, - .VRANGEPS = { 1958, 3}, - .VRANGEPD = { 1961, 3}, - .VRANGESS = { 1964, 1}, - .VRANGESD = { 1965, 1}, - .VREDUCEPS = { 1966, 3}, - .VREDUCEPD = { 1969, 3}, - .VREDUCESS = { 1972, 1}, - .VREDUCESD = { 1973, 1}, - .VRNDSCALEPS = { 1974, 3}, - .VRNDSCALEPD = { 1977, 3}, - .VRNDSCALESS = { 1980, 1}, - .VRNDSCALESD = { 1981, 1}, - .VRSQRT14PS = { 1982, 3}, - .VRSQRT14PD = { 1985, 3}, - .VRSQRT14SS = { 1988, 1}, - .VRSQRT14SD = { 1989, 1}, - .VRCP14PS = { 1990, 3}, - .VRCP14PD = { 1993, 3}, - .VRCP14SS = { 1996, 1}, - .VRCP14SD = { 1997, 1}, - .VSCALEFPS = { 1998, 3}, - .VSCALEFPD = { 2001, 3}, - .VSCALEFSS = { 2004, 1}, - .VSCALEFSD = { 2005, 1}, - .VGETEXPPS = { 2006, 3}, - .VGETEXPPD = { 2009, 3}, - .VGETEXPSS = { 2012, 1}, - .VGETEXPSD = { 2013, 1}, - .VGETMANTPS = { 2014, 3}, - .VGETMANTPD = { 2017, 3}, - .VGETMANTSS = { 2020, 1}, - .VGETMANTSD = { 2021, 1}, - .VFIXUPIMMPS = { 2022, 3}, - .VFIXUPIMMPD = { 2025, 3}, - .VFIXUPIMMSS = { 2028, 1}, - .VFIXUPIMMSD = { 2029, 1}, - .VFPCLASSPS = { 2030, 3}, - .VFPCLASSPD = { 2033, 3}, - .VFPCLASSSS = { 2036, 1}, - .VFPCLASSSD = { 2037, 1}, - .VALIGNQ = { 2038, 3}, - .VALIGND = { 2041, 3}, - .VDBPSADBW = { 2044, 3}, - .VPTERNLOGD = { 2047, 3}, - .VPTERNLOGQ = { 2050, 3}, - .VPDPWSSD = { 2053, 3}, - .VPMULTISHIFTQB = { 2056, 3}, - .KADDW = { 2059, 1}, - .KADDB = { 2060, 1}, - .KADDQ = { 2061, 1}, - .KADDD = { 2062, 1}, - .KANDW = { 2063, 1}, - .KANDB = { 2064, 1}, - .KANDQ = { 2065, 1}, - .KANDD = { 2066, 1}, - .KANDNW = { 2067, 1}, - .KANDNB = { 2068, 1}, - .KANDNQ = { 2069, 1}, - .KANDND = { 2070, 1}, - .KMOVW = { 2071, 4}, - .KMOVB = { 2075, 4}, - .KMOVQ = { 2079, 4}, - .KMOVD = { 2083, 4}, - .KNOTW = { 2087, 1}, - .KNOTB = { 2088, 1}, - .KNOTQ = { 2089, 1}, - .KNOTD = { 2090, 1}, - .KORW = { 2091, 1}, - .KORB = { 2092, 1}, - .KORQ = { 2093, 1}, - .KORD = { 2094, 1}, - .KORTESTW = { 2095, 1}, - .KORTESTB = { 2096, 1}, - .KORTESTQ = { 2097, 1}, - .KORTESTD = { 2098, 1}, - .KSHIFTLW = { 2099, 1}, - .KSHIFTLB = { 2100, 1}, - .KSHIFTLQ = { 2101, 1}, - .KSHIFTLD = { 2102, 1}, - .KSHIFTRW = { 2103, 1}, - .KSHIFTRB = { 2104, 1}, - .KSHIFTRQ = { 2105, 1}, - .KSHIFTRD = { 2106, 1}, - .KTESTW = { 2107, 1}, - .KTESTB = { 2108, 1}, - .KTESTQ = { 2109, 1}, - .KTESTD = { 2110, 1}, - .KUNPCKBW = { 2111, 1}, - .KUNPCKWD = { 2112, 1}, - .KUNPCKDQ = { 2113, 1}, - .KXNORW = { 2114, 1}, - .KXNORB = { 2115, 1}, - .KXNORQ = { 2116, 1}, - .KXNORD = { 2117, 1}, - .KXORW = { 2118, 1}, - .KXORB = { 2119, 1}, - .KXORQ = { 2120, 1}, - .KXORD = { 2121, 1}, - .FADD = { 2122, 4}, - .FADDP = { 2126, 2}, - .FIADD = { 2128, 2}, - .FSUB = { 2130, 4}, - .FSUBP = { 2134, 2}, - .FISUB = { 2136, 2}, - .FSUBR = { 2138, 4}, - .FSUBRP = { 2142, 2}, - .FISUBR = { 2144, 2}, - .FMUL = { 2146, 4}, - .FMULP = { 2150, 2}, - .FIMUL = { 2152, 2}, - .FDIV = { 2154, 4}, - .FDIVP = { 2158, 2}, - .FIDIV = { 2160, 2}, - .FDIVR = { 2162, 4}, - .FDIVRP = { 2166, 2}, - .FIDIVR = { 2168, 2}, - .FSQRT = { 2170, 1}, - .FABS = { 2171, 1}, - .FCHS = { 2172, 1}, - .FPREM = { 2173, 1}, - .FPREM1 = { 2174, 1}, - .FRNDINT = { 2175, 1}, - .FSCALE = { 2176, 1}, - .FXTRACT = { 2177, 1}, - .FXAM = { 2178, 1}, - .FLD = { 2179, 4}, - .FILD = { 2183, 3}, - .FBLD = { 2186, 1}, - .FST = { 2187, 3}, - .FSTP = { 2190, 4}, - .FIST = { 2194, 2}, - .FISTP = { 2196, 3}, - .FISTTP = { 2199, 3}, - .FBSTP = { 2202, 1}, - .FXCH = { 2203, 2}, - .FCMOVB = { 2205, 1}, - .FCMOVE = { 2206, 1}, - .FCMOVBE = { 2207, 1}, - .FCMOVU = { 2208, 1}, - .FCMOVNB = { 2209, 1}, - .FCMOVNE = { 2210, 1}, - .FCMOVNBE = { 2211, 1}, - .FCMOVNU = { 2212, 1}, - .FCOM = { 2213, 4}, - .FCOMP = { 2217, 4}, - .FCOMPP = { 2221, 1}, - .FICOM = { 2222, 2}, - .FICOMP = { 2224, 2}, - .FCOMI = { 2226, 1}, - .FCOMIP = { 2227, 1}, - .FUCOMI = { 2228, 1}, - .FUCOMIP = { 2229, 1}, - .FUCOM = { 2230, 2}, - .FUCOMP = { 2232, 2}, - .FUCOMPP = { 2234, 1}, - .FTST = { 2235, 1}, - .FLDZ = { 2236, 1}, - .FLD1 = { 2237, 1}, - .FLDPI = { 2238, 1}, - .FLDL2T = { 2239, 1}, - .FLDL2E = { 2240, 1}, - .FLDLG2 = { 2241, 1}, - .FLDLN2 = { 2242, 1}, - .FSIN = { 2243, 1}, - .FCOS = { 2244, 1}, - .FSINCOS = { 2245, 1}, - .FPTAN = { 2246, 1}, - .FPATAN = { 2247, 1}, - .F2XM1 = { 2248, 1}, - .FYL2X = { 2249, 1}, - .FYL2XP1 = { 2250, 1}, - .FINIT = { 2251, 1}, - .FNINIT = { 2252, 1}, - .FINCSTP = { 2253, 1}, - .FDECSTP = { 2254, 1}, - .FFREE = { 2255, 1}, - .FFREEP = { 2256, 1}, - .FNOP = { 2257, 1}, - .FWAIT = { 2258, 1}, - .FCLEX = { 2259, 1}, - .FNCLEX = { 2260, 1}, - .FSTCW = { 2261, 1}, - .FNSTCW = { 2262, 1}, - .FLDCW = { 2263, 1}, - .FSTENV = { 2264, 1}, - .FNSTENV = { 2265, 1}, - .FLDENV = { 2266, 1}, - .FSAVE = { 2267, 1}, - .FNSAVE = { 2268, 1}, - .FRSTOR = { 2269, 1}, - .FSTSW = { 2270, 2}, - .FNSTSW = { 2272, 2}, - .FXSAVE = { 2274, 1}, - .FXSAVE64 = { 2275, 1}, - .FXRSTOR = { 2276, 1}, - .FXRSTOR64 = { 2277, 1}, - .LGDT = { 2278, 2}, - .SGDT = { 2280, 2}, - .LIDT = { 2282, 2}, - .SIDT = { 2284, 2}, - .LLDT = { 2286, 1}, - .SLDT = { 2287, 3}, - .LTR = { 2290, 1}, - .STR = { 2291, 3}, - .LMSW = { 2294, 1}, - .SMSW = { 2295, 3}, - .CLTS = { 2298, 1}, - .ARPL = { 2299, 1}, - .LAR = { 2300, 3}, - .LSL = { 2303, 3}, - .VERR = { 2306, 1}, - .VERW = { 2307, 1}, - .INVD = { 2308, 1}, - .WBINVD = { 2309, 1}, - .INVLPG = { 2310, 1}, - .INVPCID = { 2311, 2}, - .RSM = { 2313, 1}, - .RDMSR = { 2314, 1}, - .WRMSR = { 2315, 1}, - .VMCALL = { 2316, 1}, - .VMLAUNCH = { 2317, 1}, - .VMRESUME = { 2318, 1}, - .VMXOFF = { 2319, 1}, - .VMXON = { 2320, 1}, - .VMCLEAR = { 2321, 1}, - .VMPTRLD = { 2322, 1}, - .VMPTRST = { 2323, 1}, - .VMREAD = { 2324, 1}, - .VMWRITE = { 2325, 1}, - .VMFUNC = { 2326, 1}, - .INVEPT = { 2327, 1}, - .INVVPID = { 2328, 1}, - .ENCLS = { 2329, 1}, - .ENCLU = { 2330, 1}, - .ENCLV = { 2331, 1}, - .RDPKRU = { 2332, 1}, - .WRPKRU = { 2333, 1}, - .INCSSPD = { 2334, 1}, - .INCSSPQ = { 2335, 1}, - .RDSSPD = { 2336, 1}, - .RDSSPQ = { 2337, 1}, - .SAVEPREVSSP = { 2338, 1}, - .RSTORSSP = { 2339, 1}, - .WRSSD = { 2340, 1}, - .WRSSQ = { 2341, 1}, - .WRUSSD = { 2342, 1}, - .WRUSSQ = { 2343, 1}, - .SETSSBSY = { 2344, 1}, - .CLRSSBSY = { 2345, 1}, - .ENDBR64 = { 2346, 1}, - .ENDBR32 = { 2347, 1}, - .XSAVE = { 2348, 1}, - .XSAVE64 = { 2349, 1}, - .XRSTOR = { 2350, 1}, - .XRSTOR64 = { 2351, 1}, - .XSAVEOPT = { 2352, 1}, - .XSAVEOPT64 = { 2353, 1}, - .XSAVEC = { 2354, 1}, - .XSAVEC64 = { 2355, 1}, - .XSAVES = { 2356, 1}, - .XSAVES64 = { 2357, 1}, - .XRSTORS = { 2358, 1}, - .XRSTORS64 = { 2359, 1}, - .PREFETCHT0 = { 2360, 1}, - .PREFETCHT1 = { 2361, 1}, - .PREFETCHT2 = { 2362, 1}, - .PREFETCHNTA = { 2363, 1}, - .PREFETCHW = { 2364, 1}, - .CLFLUSHOPT = { 2365, 1}, - .CLWB = { 2366, 1}, - .CLDEMOTE = { 2367, 1}, - .BSWAP = { 2368, 2}, - .CMPXCHG = { 2370, 4}, - .CMPXCHG8B = { 2374, 1}, - .CMPXCHG16B = { 2375, 1}, - .XADD = { 2376, 4}, - .BOUND = { 2380, 2}, - .ENTER = { 2382, 1}, - .LEAVE = { 2383, 1}, - .XLAT = { 2384, 1}, - .XLATB = { 2385, 1}, - .MOVBE = { 2386, 6}, - .RDRAND = { 2392, 3}, - .RDSEED = { 2395, 3}, - .SWAPGS = { 2398, 1}, - .MONITOR = { 2399, 1}, - .MWAIT = { 2400, 1}, - .CLAC = { 2401, 1}, - .STAC = { 2402, 1}, - .RDFSBASE = { 2403, 2}, - .RDGSBASE = { 2405, 2}, - .WRFSBASE = { 2407, 2}, - .WRGSBASE = { 2409, 2}, - .PTWRITE = { 2411, 2}, - .RDPID = { 2413, 1}, - .WBNOINVD = { 2414, 1}, - .SERIALIZE = { 2415, 1}, - .PREFETCH = { 2416, 1}, - .IN = { 2417, 6}, - .OUT = { 2423, 6}, - .TPAUSE = { 2429, 1}, - .UMONITOR = { 2430, 1}, - .UMWAIT = { 2431, 1}, - .MOVDIRI = { 2432, 2}, - .MOVDIR64B = { 2434, 1}, - .ENQCMD = { 2435, 1}, - .ENQCMDS = { 2436, 1}, - .AADD = { 2437, 2}, - .AAND = { 2439, 2}, - .AOR = { 2441, 2}, - .AXOR = { 2443, 2}, - .XEND = { 2445, 1}, - .XTEST = { 2446, 1}, - .VMRUN = { 2447, 1}, - .VMMCALL = { 2448, 1}, - .VMLOAD = { 2449, 1}, - .VMSAVE = { 2450, 1}, - .STGI = { 2451, 1}, - .CLGI = { 2452, 1}, - .SKINIT = { 2453, 1}, - .INVLPGA = { 2454, 1}, - .INVLPGB = { 2455, 1}, - .TLBSYNC = { 2456, 1}, - .PVALIDATE = { 2457, 1}, - .RMPADJUST = { 2458, 1}, - .RMPUPDATE = { 2459, 1}, - .PSMASH = { 2460, 1}, - .CLZERO = { 2461, 1}, - .MONITORX = { 2462, 1}, - .MWAITX = { 2463, 1}, - .RDPRU = { 2464, 1}, - .MCOMMIT = { 2465, 1}, + .SAL = { 322, 12}, + .ROL = { 334, 12}, + .ROR = { 346, 12}, + .RCL = { 358, 12}, + .RCR = { 370, 12}, + .SHLD = { 382, 6}, + .SHRD = { 388, 6}, + .BT = { 394, 6}, + .BTS = { 400, 6}, + .BTR = { 406, 6}, + .BTC = { 412, 6}, + .BSF = { 418, 3}, + .BSR = { 421, 3}, + .POPCNT = { 424, 3}, + .LZCNT = { 427, 3}, + .TZCNT = { 430, 3}, + .JMP = { 433, 6}, + .JA = { 439, 2}, + .JAE = { 441, 2}, + .JB = { 443, 2}, + .JBE = { 445, 2}, + .JC = { 447, 2}, + .JE = { 449, 2}, + .JZ = { 451, 2}, + .JG = { 453, 2}, + .JGE = { 455, 2}, + .JL = { 457, 2}, + .JLE = { 459, 2}, + .JNA = { 461, 2}, + .JNAE = { 463, 2}, + .JNB = { 465, 2}, + .JNBE = { 467, 2}, + .JNC = { 469, 2}, + .JNE = { 471, 2}, + .JNZ = { 473, 2}, + .JNG = { 475, 2}, + .JNGE = { 477, 2}, + .JNL = { 479, 2}, + .JNLE = { 481, 2}, + .JNO = { 483, 2}, + .JNP = { 485, 2}, + .JNS = { 487, 2}, + .JO = { 489, 2}, + .JP = { 491, 2}, + .JPE = { 493, 2}, + .JPO = { 495, 2}, + .JS = { 497, 2}, + .JCXZ = { 499, 1}, + .JECXZ = { 500, 1}, + .JRCXZ = { 501, 1}, + .LOOP = { 502, 1}, + .LOOPE = { 503, 1}, + .LOOPNE = { 504, 1}, + .CALL = { 505, 5}, + .RET = { 510, 2}, + .IRET = { 512, 1}, + .IRETD = { 513, 1}, + .IRETQ = { 514, 1}, + .INT = { 515, 1}, + .INT3 = { 516, 1}, + .INTO = { 517, 1}, + .SYSCALL = { 518, 1}, + .SYSRET = { 519, 1}, + .SYSENTER = { 520, 1}, + .SYSEXIT = { 521, 1}, + .SETA = { 522, 1}, + .SETAE = { 523, 1}, + .SETB = { 524, 1}, + .SETBE = { 525, 1}, + .SETC = { 526, 1}, + .SETE = { 527, 1}, + .SETG = { 528, 1}, + .SETGE = { 529, 1}, + .SETL = { 530, 1}, + .SETLE = { 531, 1}, + .SETNA = { 532, 1}, + .SETNAE = { 533, 1}, + .SETNB = { 534, 1}, + .SETNBE = { 535, 1}, + .SETNC = { 536, 1}, + .SETNE = { 537, 1}, + .SETNG = { 538, 1}, + .SETNGE = { 539, 1}, + .SETNL = { 540, 1}, + .SETNLE = { 541, 1}, + .SETNO = { 542, 1}, + .SETNP = { 543, 1}, + .SETNS = { 544, 1}, + .SETNZ = { 545, 1}, + .SETO = { 546, 1}, + .SETP = { 547, 1}, + .SETPE = { 548, 1}, + .SETPO = { 549, 1}, + .SETS = { 550, 1}, + .SETZ = { 551, 1}, + .CMOVA = { 552, 3}, + .CMOVAE = { 555, 3}, + .CMOVB = { 558, 3}, + .CMOVBE = { 561, 3}, + .CMOVC = { 564, 3}, + .CMOVE = { 567, 3}, + .CMOVG = { 570, 3}, + .CMOVGE = { 573, 3}, + .CMOVL = { 576, 3}, + .CMOVLE = { 579, 3}, + .CMOVNA = { 582, 3}, + .CMOVNAE = { 585, 3}, + .CMOVNB = { 588, 3}, + .CMOVNBE = { 591, 3}, + .CMOVNC = { 594, 3}, + .CMOVNE = { 597, 3}, + .CMOVNG = { 600, 3}, + .CMOVNGE = { 603, 3}, + .CMOVNL = { 606, 3}, + .CMOVNLE = { 609, 3}, + .CMOVNO = { 612, 3}, + .CMOVNP = { 615, 3}, + .CMOVNS = { 618, 3}, + .CMOVNZ = { 621, 3}, + .CMOVO = { 624, 3}, + .CMOVP = { 627, 3}, + .CMOVPE = { 630, 3}, + .CMOVPO = { 633, 3}, + .CMOVS = { 636, 3}, + .CMOVZ = { 639, 3}, + .MOVS = { 642, 1}, + .MOVSB = { 643, 1}, + .MOVSW = { 644, 1}, + .MOVSD = { 645, 3}, + .MOVSQ = { 648, 1}, + .CMPS = { 649, 1}, + .CMPSB = { 650, 1}, + .CMPSW = { 651, 1}, + .CMPSD = { 652, 2}, + .CMPSQ = { 654, 1}, + .SCAS = { 655, 1}, + .SCASB = { 656, 1}, + .SCASW = { 657, 1}, + .SCASD = { 658, 1}, + .SCASQ = { 659, 1}, + .LODS = { 660, 1}, + .LODSB = { 661, 1}, + .LODSW = { 662, 1}, + .LODSD = { 663, 1}, + .LODSQ = { 664, 1}, + .STOS = { 665, 1}, + .STOSB = { 666, 1}, + .STOSW = { 667, 1}, + .STOSD = { 668, 1}, + .STOSQ = { 669, 1}, + .CLC = { 670, 1}, + .STC = { 671, 1}, + .CMC = { 672, 1}, + .CLD = { 673, 1}, + .STD = { 674, 1}, + .CLI = { 675, 1}, + .STI = { 676, 1}, + .LAHF = { 677, 1}, + .SAHF = { 678, 1}, + .PUSHF = { 679, 1}, + .PUSHFD = { 680, 1}, + .PUSHFQ = { 681, 1}, + .POPF = { 682, 1}, + .POPFD = { 683, 1}, + .POPFQ = { 684, 1}, + .NOP = { 685, 4}, + .HLT = { 689, 1}, + .WAIT = { 690, 1}, + .LOCK = { 691, 1}, + .UD0 = { 692, 1}, + .UD1 = { 693, 1}, + .UD2 = { 694, 1}, + .CPUID = { 695, 1}, + .RDTSC = { 696, 1}, + .RDTSCP = { 697, 1}, + .RDPMC = { 698, 1}, + .XGETBV = { 699, 1}, + .XSETBV = { 700, 1}, + .CBW = { 701, 1}, + .CWDE = { 702, 1}, + .CDQE = { 703, 1}, + .CWD = { 704, 1}, + .CDQ = { 705, 1}, + .CQO = { 706, 1}, + .ANDN = { 707, 2}, + .BEXTR = { 709, 2}, + .BLSI = { 711, 2}, + .BLSMSK = { 713, 2}, + .BLSR = { 715, 2}, + .BZHI = { 717, 2}, + .PDEP = { 719, 2}, + .PEXT = { 721, 2}, + .RORX = { 723, 2}, + .SARX = { 725, 2}, + .SHLX = { 727, 2}, + .SHRX = { 729, 2}, + .MULX = { 731, 2}, + .ADCX = { 733, 2}, + .ADOX = { 735, 2}, + .MOVAPS = { 737, 2}, + .MOVUPS = { 739, 2}, + .MOVAPD = { 741, 2}, + .MOVUPD = { 743, 2}, + .MOVSS = { 745, 2}, + .MOVDQA = { 747, 2}, + .MOVDQU = { 749, 2}, + .MOVQ = { 751, 6}, + .MOVD = { 757, 4}, + .MOVLPS = { 761, 2}, + .MOVHPS = { 763, 2}, + .MOVLPD = { 765, 2}, + .MOVHPD = { 767, 2}, + .MOVLHPS = { 769, 1}, + .MOVHLPS = { 770, 1}, + .MOVMSKPS = { 771, 2}, + .MOVMSKPD = { 773, 2}, + .MOVNTPS = { 775, 1}, + .MOVNTPD = { 776, 1}, + .MOVNTDQ = { 777, 1}, + .MOVNTDQA = { 778, 1}, + .ADDPS = { 779, 1}, + .ADDPD = { 780, 1}, + .ADDSS = { 781, 1}, + .ADDSD = { 782, 1}, + .SUBPS = { 783, 1}, + .SUBPD = { 784, 1}, + .SUBSS = { 785, 1}, + .SUBSD = { 786, 1}, + .MULPS = { 787, 1}, + .MULPD = { 788, 1}, + .MULSS = { 789, 1}, + .MULSD = { 790, 1}, + .DIVPS = { 791, 1}, + .DIVPD = { 792, 1}, + .DIVSS = { 793, 1}, + .DIVSD = { 794, 1}, + .SQRTPS = { 795, 1}, + .SQRTPD = { 796, 1}, + .SQRTSS = { 797, 1}, + .SQRTSD = { 798, 1}, + .RCPPS = { 799, 1}, + .RCPSS = { 800, 1}, + .RSQRTPS = { 801, 1}, + .RSQRTSS = { 802, 1}, + .MAXPS = { 803, 1}, + .MAXPD = { 804, 1}, + .MAXSS = { 805, 1}, + .MAXSD = { 806, 1}, + .MINPS = { 807, 1}, + .MINPD = { 808, 1}, + .MINSS = { 809, 1}, + .MINSD = { 810, 1}, + .ANDPS = { 811, 1}, + .ANDPD = { 812, 1}, + .ANDNPS = { 813, 1}, + .ANDNPD = { 814, 1}, + .ORPS = { 815, 1}, + .ORPD = { 816, 1}, + .XORPS = { 817, 1}, + .XORPD = { 818, 1}, + .CMPPS = { 819, 1}, + .CMPPD = { 820, 1}, + .CMPSS = { 821, 1}, + .COMISS = { 822, 1}, + .COMISD = { 823, 1}, + .UCOMISS = { 824, 1}, + .UCOMISD = { 825, 1}, + .SHUFPS = { 826, 1}, + .SHUFPD = { 827, 1}, + .UNPCKLPS = { 828, 1}, + .UNPCKHPS = { 829, 1}, + .UNPCKLPD = { 830, 1}, + .UNPCKHPD = { 831, 1}, + .CVTPS2PD = { 832, 1}, + .CVTPD2PS = { 833, 1}, + .CVTSS2SD = { 834, 1}, + .CVTSD2SS = { 835, 1}, + .CVTPS2DQ = { 836, 1}, + .CVTPD2DQ = { 837, 1}, + .CVTDQ2PS = { 838, 1}, + .CVTDQ2PD = { 839, 1}, + .CVTSS2SI = { 840, 2}, + .CVTSD2SI = { 842, 2}, + .CVTSI2SS = { 844, 2}, + .CVTSI2SD = { 846, 2}, + .CVTTPS2DQ = { 848, 1}, + .CVTTPD2DQ = { 849, 1}, + .CVTTSS2SI = { 850, 2}, + .CVTTSD2SI = { 852, 2}, + .PADDB = { 854, 1}, + .PADDW = { 855, 1}, + .PADDD = { 856, 1}, + .PADDQ = { 857, 1}, + .PSUBB = { 858, 1}, + .PSUBW = { 859, 1}, + .PSUBD = { 860, 1}, + .PSUBQ = { 861, 1}, + .PADDSB = { 862, 1}, + .PADDSW = { 863, 1}, + .PADDUSB = { 864, 1}, + .PADDUSW = { 865, 1}, + .PSUBSB = { 866, 1}, + .PSUBSW = { 867, 1}, + .PSUBUSB = { 868, 1}, + .PSUBUSW = { 869, 1}, + .PMULLW = { 870, 1}, + .PMULHW = { 871, 1}, + .PMULHUW = { 872, 1}, + .PMULUDQ = { 873, 1}, + .PMADDWD = { 874, 1}, + .PAND = { 875, 1}, + .PANDN = { 876, 1}, + .POR = { 877, 1}, + .PXOR = { 878, 1}, + .PSLLW = { 879, 2}, + .PSLLD = { 881, 2}, + .PSLLQ = { 883, 2}, + .PSRLW = { 885, 2}, + .PSRLD = { 887, 2}, + .PSRLQ = { 889, 2}, + .PSRAW = { 891, 2}, + .PSRAD = { 893, 2}, + .PCMPEQB = { 895, 1}, + .PCMPEQW = { 896, 1}, + .PCMPEQD = { 897, 1}, + .PCMPGTB = { 898, 1}, + .PCMPGTW = { 899, 1}, + .PCMPGTD = { 900, 1}, + .PACKSSWB = { 901, 1}, + .PACKSSDW = { 902, 1}, + .PACKUSWB = { 903, 1}, + .PUNPCKLBW = { 904, 1}, + .PUNPCKLWD = { 905, 1}, + .PUNPCKLDQ = { 906, 1}, + .PUNPCKLQDQ = { 907, 1}, + .PUNPCKHBW = { 908, 1}, + .PUNPCKHWD = { 909, 1}, + .PUNPCKHDQ = { 910, 1}, + .PUNPCKHQDQ = { 911, 1}, + .PSHUFD = { 912, 1}, + .PSHUFHW = { 913, 1}, + .PSHUFLW = { 914, 1}, + .PSHUFW = { 915, 1}, + .PEXTRW = { 916, 2}, + .PINSRW = { 918, 2}, + .PMOVMSKB = { 920, 2}, + .PAVGB = { 922, 1}, + .PAVGW = { 923, 1}, + .PMAXUB = { 924, 1}, + .PMAXSW = { 925, 1}, + .PMINUB = { 926, 1}, + .PMINSW = { 927, 1}, + .PSADBW = { 928, 1}, + .MASKMOVDQU = { 929, 1}, + .LFENCE = { 930, 1}, + .SFENCE = { 931, 1}, + .MFENCE = { 932, 1}, + .PAUSE = { 933, 1}, + .CLFLUSH = { 934, 1}, + .ADDSUBPS = { 935, 1}, + .ADDSUBPD = { 936, 1}, + .HADDPS = { 937, 1}, + .HADDPD = { 938, 1}, + .HSUBPS = { 939, 1}, + .HSUBPD = { 940, 1}, + .MOVDDUP = { 941, 1}, + .MOVSLDUP = { 942, 1}, + .MOVSHDUP = { 943, 1}, + .LDDQU = { 944, 1}, + .PSHUFB = { 945, 1}, + .PHADDW = { 946, 1}, + .PHADDD = { 947, 1}, + .PHADDSW = { 948, 1}, + .PHSUBW = { 949, 1}, + .PHSUBD = { 950, 1}, + .PHSUBSW = { 951, 1}, + .PMADDUBSW = { 952, 1}, + .PMULHRSW = { 953, 1}, + .PSIGNB = { 954, 1}, + .PSIGNW = { 955, 1}, + .PSIGND = { 956, 1}, + .PABSB = { 957, 1}, + .PABSW = { 958, 1}, + .PABSD = { 959, 1}, + .PALIGNR = { 960, 1}, + .BLENDPS = { 961, 1}, + .BLENDPD = { 962, 1}, + .BLENDVPS = { 963, 1}, + .BLENDVPD = { 964, 1}, + .PBLENDW = { 965, 1}, + .PBLENDVB = { 966, 1}, + .DPPS = { 967, 1}, + .DPPD = { 968, 1}, + .EXTRACTPS = { 969, 1}, + .INSERTPS = { 970, 1}, + .MPSADBW = { 971, 1}, + .PACKUSDW = { 972, 1}, + .PEXTRB = { 973, 1}, + .PEXTRD = { 974, 1}, + .PEXTRQ = { 975, 1}, + .PHMINPOSUW = { 976, 1}, + .PINSRB = { 977, 1}, + .PINSRD = { 978, 1}, + .PINSRQ = { 979, 1}, + .PMAXSB = { 980, 1}, + .PMAXSD = { 981, 1}, + .PMAXUW = { 982, 1}, + .PMAXUD = { 983, 1}, + .PMINSB = { 984, 1}, + .PMINSD = { 985, 1}, + .PMINUW = { 986, 1}, + .PMINUD = { 987, 1}, + .PMOVSXBW = { 988, 1}, + .PMOVSXBD = { 989, 1}, + .PMOVSXBQ = { 990, 1}, + .PMOVSXWD = { 991, 1}, + .PMOVSXWQ = { 992, 1}, + .PMOVSXDQ = { 993, 1}, + .PMOVZXBW = { 994, 1}, + .PMOVZXBD = { 995, 1}, + .PMOVZXBQ = { 996, 1}, + .PMOVZXWD = { 997, 1}, + .PMOVZXWQ = { 998, 1}, + .PMOVZXDQ = { 999, 1}, + .PMULDQ = { 1000, 1}, + .PMULLD = { 1001, 1}, + .PTEST = { 1002, 1}, + .ROUNDPS = { 1003, 1}, + .ROUNDPD = { 1004, 1}, + .ROUNDSS = { 1005, 1}, + .ROUNDSD = { 1006, 1}, + .PCMPEQQ = { 1007, 1}, + .CRC32 = { 1008, 5}, + .PCMPESTRI = { 1013, 1}, + .PCMPESTRM = { 1014, 1}, + .PCMPISTRI = { 1015, 1}, + .PCMPISTRM = { 1016, 1}, + .PCMPGTQ = { 1017, 1}, + .PCLMULQDQ = { 1018, 1}, + .AESDEC = { 1019, 1}, + .AESDECLAST = { 1020, 1}, + .AESENC = { 1021, 1}, + .AESENCLAST = { 1022, 1}, + .AESIMC = { 1023, 1}, + .AESKEYGENASSIST = { 1024, 1}, + .SHA1MSG1 = { 1025, 1}, + .SHA1MSG2 = { 1026, 1}, + .SHA1NEXTE = { 1027, 1}, + .SHA1RNDS4 = { 1028, 1}, + .SHA256MSG1 = { 1029, 1}, + .SHA256MSG2 = { 1030, 1}, + .SHA256RNDS2 = { 1031, 1}, + .VADDPS = { 1032, 2}, + .VADDPD = { 1034, 2}, + .VADDSS = { 1036, 1}, + .VADDSD = { 1037, 1}, + .VSUBPS = { 1038, 2}, + .VSUBPD = { 1040, 2}, + .VSUBSS = { 1042, 1}, + .VSUBSD = { 1043, 1}, + .VMULPS = { 1044, 2}, + .VMULPD = { 1046, 2}, + .VMULSS = { 1048, 1}, + .VMULSD = { 1049, 1}, + .VDIVPS = { 1050, 2}, + .VDIVPD = { 1052, 2}, + .VDIVSS = { 1054, 1}, + .VDIVSD = { 1055, 1}, + .VSQRTPS = { 1056, 2}, + .VSQRTPD = { 1058, 2}, + .VSQRTSS = { 1060, 1}, + .VSQRTSD = { 1061, 1}, + .VRCPPS = { 1062, 2}, + .VRCPSS = { 1064, 1}, + .VRSQRTPS = { 1065, 2}, + .VRSQRTSS = { 1067, 1}, + .VMAXPS = { 1068, 2}, + .VMAXPD = { 1070, 2}, + .VMAXSS = { 1072, 1}, + .VMAXSD = { 1073, 1}, + .VMINPS = { 1074, 2}, + .VMINPD = { 1076, 2}, + .VMINSS = { 1078, 1}, + .VMINSD = { 1079, 1}, + .VANDPS = { 1080, 2}, + .VANDPD = { 1082, 2}, + .VANDNPS = { 1084, 2}, + .VANDNPD = { 1086, 2}, + .VORPS = { 1088, 2}, + .VORPD = { 1090, 2}, + .VXORPS = { 1092, 2}, + .VXORPD = { 1094, 2}, + .VCMPPS = { 1096, 2}, + .VCMPPD = { 1098, 2}, + .VCMPSS = { 1100, 1}, + .VCMPSD = { 1101, 1}, + .VCOMISS = { 1102, 1}, + .VCOMISD = { 1103, 1}, + .VUCOMISS = { 1104, 1}, + .VUCOMISD = { 1105, 1}, + .VSHUFPS = { 1106, 2}, + .VSHUFPD = { 1108, 2}, + .VUNPCKLPS = { 1110, 2}, + .VUNPCKHPS = { 1112, 2}, + .VUNPCKLPD = { 1114, 2}, + .VUNPCKHPD = { 1116, 2}, + .VBLENDPS = { 1118, 2}, + .VBLENDPD = { 1120, 2}, + .VBLENDVPS = { 1122, 2}, + .VBLENDVPD = { 1124, 2}, + .VDPPS = { 1126, 2}, + .VDPPD = { 1128, 1}, + .VROUNDPS = { 1129, 2}, + .VROUNDPD = { 1131, 2}, + .VROUNDSS = { 1133, 1}, + .VROUNDSD = { 1134, 1}, + .VEXTRACTPS = { 1135, 1}, + .VINSERTPS = { 1136, 1}, + .VMOVAPS = { 1137, 4}, + .VMOVUPS = { 1141, 4}, + .VMOVAPD = { 1145, 4}, + .VMOVUPD = { 1149, 4}, + .VMOVSS = { 1153, 3}, + .VMOVSD = { 1156, 3}, + .VMOVDQA = { 1159, 4}, + .VMOVDQU = { 1163, 4}, + .VMOVQ = { 1167, 4}, + .VMOVD = { 1171, 2}, + .VMOVLPS = { 1173, 2}, + .VMOVHPS = { 1175, 2}, + .VMOVLPD = { 1177, 2}, + .VMOVHPD = { 1179, 2}, + .VMOVLHPS = { 1181, 1}, + .VMOVHLPS = { 1182, 1}, + .VMOVMSKPS = { 1183, 2}, + .VMOVMSKPD = { 1185, 2}, + .VMOVNTPS = { 1187, 2}, + .VMOVNTPD = { 1189, 2}, + .VMOVNTDQ = { 1191, 2}, + .VMOVNTDQA = { 1193, 2}, + .VADDSUBPS = { 1195, 2}, + .VADDSUBPD = { 1197, 2}, + .VHADDPS = { 1199, 2}, + .VHADDPD = { 1201, 2}, + .VHSUBPS = { 1203, 2}, + .VHSUBPD = { 1205, 2}, + .VLDDQU = { 1207, 2}, + .VMOVDDUP = { 1209, 2}, + .VMOVSLDUP = { 1211, 2}, + .VMOVSHDUP = { 1213, 2}, + .VPCMPESTRI = { 1215, 1}, + .VPCMPESTRM = { 1216, 1}, + .VPCMPISTRI = { 1217, 1}, + .VPCMPISTRM = { 1218, 1}, + .VPBROADCASTB = { 1219, 4}, + .VPBROADCASTW = { 1223, 4}, + .VPBROADCASTD = { 1227, 4}, + .VPBROADCASTQ = { 1231, 4}, + .VCVTPS2PD = { 1235, 2}, + .VCVTPD2PS = { 1237, 2}, + .VCVTSS2SD = { 1239, 1}, + .VCVTSD2SS = { 1240, 1}, + .VCVTPS2DQ = { 1241, 2}, + .VCVTPD2DQ = { 1243, 2}, + .VCVTDQ2PS = { 1245, 2}, + .VCVTDQ2PD = { 1247, 2}, + .VCVTSS2SI = { 1249, 2}, + .VCVTSD2SI = { 1251, 2}, + .VCVTSI2SS = { 1253, 2}, + .VCVTSI2SD = { 1255, 2}, + .VCVTTPS2DQ = { 1257, 2}, + .VCVTTPD2DQ = { 1259, 2}, + .VCVTTSS2SI = { 1261, 2}, + .VCVTTSD2SI = { 1263, 2}, + .VPADDB = { 1265, 2}, + .VPADDW = { 1267, 2}, + .VPADDD = { 1269, 2}, + .VPADDQ = { 1271, 2}, + .VPSUBB = { 1273, 2}, + .VPSUBW = { 1275, 2}, + .VPSUBD = { 1277, 2}, + .VPSUBQ = { 1279, 2}, + .VPMULLW = { 1281, 2}, + .VPMULHW = { 1283, 2}, + .VPMULHUW = { 1285, 2}, + .VPMULUDQ = { 1287, 2}, + .VPMADDWD = { 1289, 2}, + .VPAND = { 1291, 2}, + .VPANDN = { 1293, 2}, + .VPOR = { 1295, 2}, + .VPXOR = { 1297, 2}, + .VPSLLW = { 1299, 4}, + .VPSLLD = { 1303, 4}, + .VPSLLQ = { 1307, 4}, + .VPSRLW = { 1311, 4}, + .VPSRLD = { 1315, 4}, + .VPSRLQ = { 1319, 4}, + .VPSRAW = { 1323, 4}, + .VPSRAD = { 1327, 4}, + .VPCMPEQB = { 1331, 2}, + .VPCMPEQW = { 1333, 2}, + .VPCMPEQD = { 1335, 2}, + .VPCMPEQQ = { 1337, 2}, + .VPCMPGTB = { 1339, 2}, + .VPCMPGTW = { 1341, 2}, + .VPCMPGTD = { 1343, 2}, + .VPCMPGTQ = { 1345, 2}, + .VPACKSSWB = { 1347, 2}, + .VPACKSSDW = { 1349, 2}, + .VPACKUSWB = { 1351, 2}, + .VPACKUSDW = { 1353, 2}, + .VPUNPCKLBW = { 1355, 2}, + .VPUNPCKLWD = { 1357, 2}, + .VPUNPCKLDQ = { 1359, 2}, + .VPUNPCKLQDQ = { 1361, 2}, + .VPUNPCKHBW = { 1363, 2}, + .VPUNPCKHWD = { 1365, 2}, + .VPUNPCKHDQ = { 1367, 2}, + .VPUNPCKHQDQ = { 1369, 2}, + .VPSHUFD = { 1371, 2}, + .VPSHUFHW = { 1373, 2}, + .VPSHUFLW = { 1375, 2}, + .VPEXTRB = { 1377, 1}, + .VPEXTRW = { 1378, 2}, + .VPEXTRD = { 1380, 1}, + .VPEXTRQ = { 1381, 1}, + .VPINSRB = { 1382, 1}, + .VPINSRW = { 1383, 1}, + .VPINSRD = { 1384, 1}, + .VPINSRQ = { 1385, 1}, + .VPMOVMSKB = { 1386, 2}, + .VPTEST = { 1388, 2}, + .VPSHUFB = { 1390, 2}, + .VPHADDW = { 1392, 2}, + .VPHADDD = { 1394, 2}, + .VPHADDSW = { 1396, 2}, + .VPHSUBW = { 1398, 2}, + .VPHSUBD = { 1400, 2}, + .VPHSUBSW = { 1402, 2}, + .VPMADDUBSW = { 1404, 2}, + .VPMULHRSW = { 1406, 2}, + .VPSIGNB = { 1408, 2}, + .VPSIGNW = { 1410, 2}, + .VPSIGND = { 1412, 2}, + .VPABSB = { 1414, 2}, + .VPABSW = { 1416, 2}, + .VPABSD = { 1418, 2}, + .VPALIGNR = { 1420, 2}, + .VPBLENDW = { 1422, 2}, + .VPBLENDVB = { 1424, 2}, + .VMPSADBW = { 1426, 2}, + .VPHMINPOSUW = { 1428, 1}, + .VPMAXSB = { 1429, 2}, + .VPMAXSD = { 1431, 2}, + .VPMAXUW = { 1433, 2}, + .VPMAXUD = { 1435, 2}, + .VPMINSB = { 1437, 2}, + .VPMINSD = { 1439, 2}, + .VPMINUW = { 1441, 2}, + .VPMINUD = { 1443, 2}, + .VPMOVSXBW = { 1445, 2}, + .VPMOVSXBD = { 1447, 2}, + .VPMOVSXBQ = { 1449, 2}, + .VPMOVSXWD = { 1451, 2}, + .VPMOVSXWQ = { 1453, 2}, + .VPMOVSXDQ = { 1455, 2}, + .VPMOVZXBW = { 1457, 2}, + .VPMOVZXBD = { 1459, 2}, + .VPMOVZXBQ = { 1461, 2}, + .VPMOVZXWD = { 1463, 2}, + .VPMOVZXWQ = { 1465, 2}, + .VPMOVZXDQ = { 1467, 2}, + .VPMULDQ = { 1469, 2}, + .VPMULLD = { 1471, 2}, + .VMASKMOVDQU = { 1473, 1}, + .VPCLMULQDQ = { 1474, 2}, + .VAESDEC = { 1476, 1}, + .VAESDECLAST = { 1477, 1}, + .VAESENC = { 1478, 1}, + .VAESENCLAST = { 1479, 1}, + .VAESIMC = { 1480, 1}, + .VAESKEYGENASSIST = { 1481, 1}, + .VBROADCASTSS = { 1482, 4}, + .VBROADCASTSD = { 1486, 2}, + .VBROADCASTF128 = { 1488, 1}, + .VEXTRACTF128 = { 1489, 1}, + .VINSERTF128 = { 1490, 1}, + .VPERM2F128 = { 1491, 1}, + .VMASKMOVPS = { 1492, 4}, + .VMASKMOVPD = { 1496, 4}, + .VTESTPS = { 1500, 2}, + .VTESTPD = { 1502, 2}, + .VZEROALL = { 1504, 1}, + .VZEROUPPER = { 1505, 1}, + .VBROADCASTI128 = { 1506, 1}, + .VEXTRACTI128 = { 1507, 1}, + .VINSERTI128 = { 1508, 1}, + .VPERM2I128 = { 1509, 1}, + .VPERMD = { 1510, 1}, + .VPERMPS = { 1511, 1}, + .VPERMQ = { 1512, 1}, + .VPERMPD = { 1513, 1}, + .VPBLENDD = { 1514, 2}, + .VPSLLVD = { 1516, 2}, + .VPSLLVQ = { 1518, 2}, + .VPSRLVD = { 1520, 2}, + .VPSRLVQ = { 1522, 2}, + .VPSRAVD = { 1524, 2}, + .VPMASKMOVD = { 1526, 4}, + .VPMASKMOVQ = { 1530, 4}, + .VGATHERDPS = { 1534, 2}, + .VGATHERDPD = { 1536, 2}, + .VGATHERQPS = { 1538, 2}, + .VGATHERQPD = { 1540, 2}, + .VPGATHERDD = { 1542, 2}, + .VPGATHERDQ = { 1544, 2}, + .VPGATHERQD = { 1546, 2}, + .VPGATHERQQ = { 1548, 2}, + .VFMADD132PS = { 1550, 2}, + .VFMADD213PS = { 1552, 2}, + .VFMADD231PS = { 1554, 2}, + .VFMADD132PD = { 1556, 2}, + .VFMADD213PD = { 1558, 2}, + .VFMADD231PD = { 1560, 2}, + .VFMADD132SS = { 1562, 1}, + .VFMADD213SS = { 1563, 1}, + .VFMADD231SS = { 1564, 1}, + .VFMADD132SD = { 1565, 1}, + .VFMADD213SD = { 1566, 1}, + .VFMADD231SD = { 1567, 1}, + .VFMSUB132PS = { 1568, 2}, + .VFMSUB213PS = { 1570, 2}, + .VFMSUB231PS = { 1572, 2}, + .VFMSUB132PD = { 1574, 2}, + .VFMSUB213PD = { 1576, 2}, + .VFMSUB231PD = { 1578, 2}, + .VFMSUB132SS = { 1580, 1}, + .VFMSUB213SS = { 1581, 1}, + .VFMSUB231SS = { 1582, 1}, + .VFMSUB132SD = { 1583, 1}, + .VFMSUB213SD = { 1584, 1}, + .VFMSUB231SD = { 1585, 1}, + .VFNMADD132PS = { 1586, 2}, + .VFNMADD213PS = { 1588, 2}, + .VFNMADD231PS = { 1590, 2}, + .VFNMADD132PD = { 1592, 2}, + .VFNMADD213PD = { 1594, 2}, + .VFNMADD231PD = { 1596, 2}, + .VFNMADD132SS = { 1598, 1}, + .VFNMADD213SS = { 1599, 1}, + .VFNMADD231SS = { 1600, 1}, + .VFNMADD132SD = { 1601, 1}, + .VFNMADD213SD = { 1602, 1}, + .VFNMADD231SD = { 1603, 1}, + .VFNMSUB132PS = { 1604, 2}, + .VFNMSUB213PS = { 1606, 2}, + .VFNMSUB231PS = { 1608, 2}, + .VFNMSUB132PD = { 1610, 2}, + .VFNMSUB213PD = { 1612, 2}, + .VFNMSUB231PD = { 1614, 2}, + .VFNMSUB132SS = { 1616, 1}, + .VFNMSUB213SS = { 1617, 1}, + .VFNMSUB231SS = { 1618, 1}, + .VFNMSUB132SD = { 1619, 1}, + .VFNMSUB213SD = { 1620, 1}, + .VFNMSUB231SD = { 1621, 1}, + .VFMADDSUB132PS = { 1622, 2}, + .VFMADDSUB213PS = { 1624, 2}, + .VFMADDSUB231PS = { 1626, 2}, + .VFMADDSUB132PD = { 1628, 2}, + .VFMADDSUB213PD = { 1630, 2}, + .VFMADDSUB231PD = { 1632, 2}, + .VFMSUBADD132PS = { 1634, 2}, + .VFMSUBADD213PS = { 1636, 2}, + .VFMSUBADD231PS = { 1638, 2}, + .VFMSUBADD132PD = { 1640, 2}, + .VFMSUBADD213PD = { 1642, 2}, + .VFMSUBADD231PD = { 1644, 2}, + .VCVTPH2PS = { 1646, 3}, + .VCVTPS2PH = { 1649, 3}, + .VMOVDQA32 = { 1652, 6}, + .VMOVDQA64 = { 1658, 6}, + .VMOVDQU8 = { 1664, 6}, + .VMOVDQU16 = { 1670, 6}, + .VMOVDQU32 = { 1676, 6}, + .VMOVDQU64 = { 1682, 6}, + .VPBLENDMB = { 1688, 3}, + .VPBLENDMW = { 1691, 3}, + .VPBLENDMD = { 1694, 3}, + .VPBLENDMQ = { 1697, 3}, + .VBLENDMPS = { 1700, 3}, + .VBLENDMPD = { 1703, 3}, + .VPCMPB = { 1706, 3}, + .VPCMPUB = { 1709, 3}, + .VPCMPW = { 1712, 3}, + .VPCMPUW = { 1715, 3}, + .VPCMPD = { 1718, 3}, + .VPCMPUD = { 1721, 3}, + .VPCMPQ = { 1724, 3}, + .VPCMPUQ = { 1727, 3}, + .VPTESTMB = { 1730, 3}, + .VPTESTMW = { 1733, 3}, + .VPTESTMD = { 1736, 3}, + .VPTESTMQ = { 1739, 3}, + .VPTESTNMB = { 1742, 3}, + .VPTESTNMW = { 1745, 3}, + .VPTESTNMD = { 1748, 3}, + .VPTESTNMQ = { 1751, 3}, + .VPCOMPRESSD = { 1754, 3}, + .VPCOMPRESSQ = { 1757, 3}, + .VCOMPRESSPS = { 1760, 3}, + .VCOMPRESSPD = { 1763, 3}, + .VPEXPANDD = { 1766, 3}, + .VPEXPANDQ = { 1769, 3}, + .VEXPANDPS = { 1772, 3}, + .VEXPANDPD = { 1775, 3}, + .VPCONFLICTD = { 1778, 3}, + .VPCONFLICTQ = { 1781, 3}, + .VPLZCNTD = { 1784, 3}, + .VPLZCNTQ = { 1787, 3}, + .VPERMI2B = { 1790, 3}, + .VPERMI2W = { 1793, 3}, + .VPERMI2D = { 1796, 3}, + .VPERMI2Q = { 1799, 3}, + .VPERMI2PS = { 1802, 3}, + .VPERMI2PD = { 1805, 3}, + .VPERMT2B = { 1808, 3}, + .VPERMT2W = { 1811, 3}, + .VPERMT2D = { 1814, 3}, + .VPERMT2Q = { 1817, 3}, + .VPERMT2PS = { 1820, 3}, + .VPERMT2PD = { 1823, 3}, + .VPERMB = { 1826, 3}, + .VPERMW = { 1829, 3}, + .VPMOVB2M = { 1832, 3}, + .VPMOVW2M = { 1835, 3}, + .VPMOVD2M = { 1838, 3}, + .VPMOVQ2M = { 1841, 3}, + .VPMOVM2B = { 1844, 3}, + .VPMOVM2W = { 1847, 3}, + .VPMOVM2D = { 1850, 3}, + .VPMOVM2Q = { 1853, 3}, + .VPMOVQB = { 1856, 3}, + .VPMOVSQB = { 1859, 3}, + .VPMOVUSQB = { 1862, 3}, + .VPMOVQW = { 1865, 3}, + .VPMOVSQW = { 1868, 3}, + .VPMOVUSQW = { 1871, 3}, + .VPMOVQD = { 1874, 3}, + .VPMOVSQD = { 1877, 3}, + .VPMOVUSQD = { 1880, 3}, + .VPMOVDB = { 1883, 3}, + .VPMOVSDB = { 1886, 3}, + .VPMOVUSDB = { 1889, 3}, + .VPMOVDW = { 1892, 3}, + .VPMOVSDW = { 1895, 3}, + .VPMOVUSDW = { 1898, 3}, + .VPMOVWB = { 1901, 3}, + .VPMOVSWB = { 1904, 3}, + .VPMOVUSWB = { 1907, 3}, + .VPROLD = { 1910, 3}, + .VPROLQ = { 1913, 3}, + .VPROLVD = { 1916, 3}, + .VPROLVQ = { 1919, 3}, + .VPRORD = { 1922, 3}, + .VPRORQ = { 1925, 3}, + .VPRORVD = { 1928, 3}, + .VPRORVQ = { 1931, 3}, + .VPSCATTERDD = { 1934, 3}, + .VPSCATTERDQ = { 1937, 3}, + .VPSCATTERQD = { 1940, 3}, + .VPSCATTERQQ = { 1943, 3}, + .VSCATTERDPS = { 1946, 3}, + .VSCATTERDPD = { 1949, 3}, + .VSCATTERQPS = { 1952, 3}, + .VSCATTERQPD = { 1955, 3}, + .VPSRAVQ = { 1958, 3}, + .VPSRAVW = { 1961, 3}, + .VPSLLVW = { 1964, 3}, + .VPSRLVW = { 1967, 3}, + .VRANGEPS = { 1970, 3}, + .VRANGEPD = { 1973, 3}, + .VRANGESS = { 1976, 1}, + .VRANGESD = { 1977, 1}, + .VREDUCEPS = { 1978, 3}, + .VREDUCEPD = { 1981, 3}, + .VREDUCESS = { 1984, 1}, + .VREDUCESD = { 1985, 1}, + .VRNDSCALEPS = { 1986, 3}, + .VRNDSCALEPD = { 1989, 3}, + .VRNDSCALESS = { 1992, 1}, + .VRNDSCALESD = { 1993, 1}, + .VRSQRT14PS = { 1994, 3}, + .VRSQRT14PD = { 1997, 3}, + .VRSQRT14SS = { 2000, 1}, + .VRSQRT14SD = { 2001, 1}, + .VRCP14PS = { 2002, 3}, + .VRCP14PD = { 2005, 3}, + .VRCP14SS = { 2008, 1}, + .VRCP14SD = { 2009, 1}, + .VSCALEFPS = { 2010, 3}, + .VSCALEFPD = { 2013, 3}, + .VSCALEFSS = { 2016, 1}, + .VSCALEFSD = { 2017, 1}, + .VGETEXPPS = { 2018, 3}, + .VGETEXPPD = { 2021, 3}, + .VGETEXPSS = { 2024, 1}, + .VGETEXPSD = { 2025, 1}, + .VGETMANTPS = { 2026, 3}, + .VGETMANTPD = { 2029, 3}, + .VGETMANTSS = { 2032, 1}, + .VGETMANTSD = { 2033, 1}, + .VFIXUPIMMPS = { 2034, 3}, + .VFIXUPIMMPD = { 2037, 3}, + .VFIXUPIMMSS = { 2040, 1}, + .VFIXUPIMMSD = { 2041, 1}, + .VFPCLASSPS = { 2042, 3}, + .VFPCLASSPD = { 2045, 3}, + .VFPCLASSSS = { 2048, 1}, + .VFPCLASSSD = { 2049, 1}, + .VALIGNQ = { 2050, 3}, + .VALIGND = { 2053, 3}, + .VDBPSADBW = { 2056, 3}, + .VPTERNLOGD = { 2059, 3}, + .VPTERNLOGQ = { 2062, 3}, + .VPDPWSSD = { 2065, 3}, + .VPMULTISHIFTQB = { 2068, 3}, + .KADDW = { 2071, 1}, + .KADDB = { 2072, 1}, + .KADDQ = { 2073, 1}, + .KADDD = { 2074, 1}, + .KANDW = { 2075, 1}, + .KANDB = { 2076, 1}, + .KANDQ = { 2077, 1}, + .KANDD = { 2078, 1}, + .KANDNW = { 2079, 1}, + .KANDNB = { 2080, 1}, + .KANDNQ = { 2081, 1}, + .KANDND = { 2082, 1}, + .KMOVW = { 2083, 4}, + .KMOVB = { 2087, 4}, + .KMOVQ = { 2091, 4}, + .KMOVD = { 2095, 4}, + .KNOTW = { 2099, 1}, + .KNOTB = { 2100, 1}, + .KNOTQ = { 2101, 1}, + .KNOTD = { 2102, 1}, + .KORW = { 2103, 1}, + .KORB = { 2104, 1}, + .KORQ = { 2105, 1}, + .KORD = { 2106, 1}, + .KORTESTW = { 2107, 1}, + .KORTESTB = { 2108, 1}, + .KORTESTQ = { 2109, 1}, + .KORTESTD = { 2110, 1}, + .KSHIFTLW = { 2111, 1}, + .KSHIFTLB = { 2112, 1}, + .KSHIFTLQ = { 2113, 1}, + .KSHIFTLD = { 2114, 1}, + .KSHIFTRW = { 2115, 1}, + .KSHIFTRB = { 2116, 1}, + .KSHIFTRQ = { 2117, 1}, + .KSHIFTRD = { 2118, 1}, + .KTESTW = { 2119, 1}, + .KTESTB = { 2120, 1}, + .KTESTQ = { 2121, 1}, + .KTESTD = { 2122, 1}, + .KUNPCKBW = { 2123, 1}, + .KUNPCKWD = { 2124, 1}, + .KUNPCKDQ = { 2125, 1}, + .KXNORW = { 2126, 1}, + .KXNORB = { 2127, 1}, + .KXNORQ = { 2128, 1}, + .KXNORD = { 2129, 1}, + .KXORW = { 2130, 1}, + .KXORB = { 2131, 1}, + .KXORQ = { 2132, 1}, + .KXORD = { 2133, 1}, + .FADD = { 2134, 4}, + .FADDP = { 2138, 2}, + .FIADD = { 2140, 2}, + .FSUB = { 2142, 4}, + .FSUBP = { 2146, 2}, + .FISUB = { 2148, 2}, + .FSUBR = { 2150, 4}, + .FSUBRP = { 2154, 2}, + .FISUBR = { 2156, 2}, + .FMUL = { 2158, 4}, + .FMULP = { 2162, 2}, + .FIMUL = { 2164, 2}, + .FDIV = { 2166, 4}, + .FDIVP = { 2170, 2}, + .FIDIV = { 2172, 2}, + .FDIVR = { 2174, 4}, + .FDIVRP = { 2178, 2}, + .FIDIVR = { 2180, 2}, + .FSQRT = { 2182, 1}, + .FABS = { 2183, 1}, + .FCHS = { 2184, 1}, + .FPREM = { 2185, 1}, + .FPREM1 = { 2186, 1}, + .FRNDINT = { 2187, 1}, + .FSCALE = { 2188, 1}, + .FXTRACT = { 2189, 1}, + .FXAM = { 2190, 1}, + .FLD = { 2191, 4}, + .FILD = { 2195, 3}, + .FBLD = { 2198, 1}, + .FST = { 2199, 3}, + .FSTP = { 2202, 4}, + .FIST = { 2206, 2}, + .FISTP = { 2208, 3}, + .FISTTP = { 2211, 3}, + .FBSTP = { 2214, 1}, + .FXCH = { 2215, 2}, + .FCMOVB = { 2217, 1}, + .FCMOVE = { 2218, 1}, + .FCMOVBE = { 2219, 1}, + .FCMOVU = { 2220, 1}, + .FCMOVNB = { 2221, 1}, + .FCMOVNE = { 2222, 1}, + .FCMOVNBE = { 2223, 1}, + .FCMOVNU = { 2224, 1}, + .FCOM = { 2225, 4}, + .FCOMP = { 2229, 4}, + .FCOMPP = { 2233, 1}, + .FICOM = { 2234, 2}, + .FICOMP = { 2236, 2}, + .FCOMI = { 2238, 1}, + .FCOMIP = { 2239, 1}, + .FUCOMI = { 2240, 1}, + .FUCOMIP = { 2241, 1}, + .FUCOM = { 2242, 2}, + .FUCOMP = { 2244, 2}, + .FUCOMPP = { 2246, 1}, + .FTST = { 2247, 1}, + .FLDZ = { 2248, 1}, + .FLD1 = { 2249, 1}, + .FLDPI = { 2250, 1}, + .FLDL2T = { 2251, 1}, + .FLDL2E = { 2252, 1}, + .FLDLG2 = { 2253, 1}, + .FLDLN2 = { 2254, 1}, + .FSIN = { 2255, 1}, + .FCOS = { 2256, 1}, + .FSINCOS = { 2257, 1}, + .FPTAN = { 2258, 1}, + .FPATAN = { 2259, 1}, + .F2XM1 = { 2260, 1}, + .FYL2X = { 2261, 1}, + .FYL2XP1 = { 2262, 1}, + .FINIT = { 2263, 1}, + .FNINIT = { 2264, 1}, + .FINCSTP = { 2265, 1}, + .FDECSTP = { 2266, 1}, + .FFREE = { 2267, 1}, + .FFREEP = { 2268, 1}, + .FNOP = { 2269, 1}, + .FWAIT = { 2270, 1}, + .FCLEX = { 2271, 1}, + .FNCLEX = { 2272, 1}, + .FSTCW = { 2273, 1}, + .FNSTCW = { 2274, 1}, + .FLDCW = { 2275, 1}, + .FSTENV = { 2276, 1}, + .FNSTENV = { 2277, 1}, + .FLDENV = { 2278, 1}, + .FSAVE = { 2279, 1}, + .FNSAVE = { 2280, 1}, + .FRSTOR = { 2281, 1}, + .FSTSW = { 2282, 2}, + .FNSTSW = { 2284, 2}, + .FXSAVE = { 2286, 1}, + .FXSAVE64 = { 2287, 1}, + .FXRSTOR = { 2288, 1}, + .FXRSTOR64 = { 2289, 1}, + .LGDT = { 2290, 2}, + .SGDT = { 2292, 2}, + .LIDT = { 2294, 2}, + .SIDT = { 2296, 2}, + .LLDT = { 2298, 1}, + .SLDT = { 2299, 3}, + .LTR = { 2302, 1}, + .STR = { 2303, 3}, + .LMSW = { 2306, 1}, + .SMSW = { 2307, 3}, + .CLTS = { 2310, 1}, + .ARPL = { 2311, 1}, + .LAR = { 2312, 3}, + .LSL = { 2315, 3}, + .VERR = { 2318, 1}, + .VERW = { 2319, 1}, + .INVD = { 2320, 1}, + .WBINVD = { 2321, 1}, + .INVLPG = { 2322, 1}, + .INVPCID = { 2323, 2}, + .RSM = { 2325, 1}, + .RDMSR = { 2326, 1}, + .WRMSR = { 2327, 1}, + .VMCALL = { 2328, 1}, + .VMLAUNCH = { 2329, 1}, + .VMRESUME = { 2330, 1}, + .VMXOFF = { 2331, 1}, + .VMXON = { 2332, 1}, + .VMCLEAR = { 2333, 1}, + .VMPTRLD = { 2334, 1}, + .VMPTRST = { 2335, 1}, + .VMREAD = { 2336, 1}, + .VMWRITE = { 2337, 1}, + .VMFUNC = { 2338, 1}, + .INVEPT = { 2339, 1}, + .INVVPID = { 2340, 1}, + .ENCLS = { 2341, 1}, + .ENCLU = { 2342, 1}, + .ENCLV = { 2343, 1}, + .RDPKRU = { 2344, 1}, + .WRPKRU = { 2345, 1}, + .INCSSPD = { 2346, 1}, + .INCSSPQ = { 2347, 1}, + .RDSSPD = { 2348, 1}, + .RDSSPQ = { 2349, 1}, + .SAVEPREVSSP = { 2350, 1}, + .RSTORSSP = { 2351, 1}, + .WRSSD = { 2352, 1}, + .WRSSQ = { 2353, 1}, + .WRUSSD = { 2354, 1}, + .WRUSSQ = { 2355, 1}, + .SETSSBSY = { 2356, 1}, + .CLRSSBSY = { 2357, 1}, + .ENDBR64 = { 2358, 1}, + .ENDBR32 = { 2359, 1}, + .XSAVE = { 2360, 1}, + .XSAVE64 = { 2361, 1}, + .XRSTOR = { 2362, 1}, + .XRSTOR64 = { 2363, 1}, + .XSAVEOPT = { 2364, 1}, + .XSAVEOPT64 = { 2365, 1}, + .XSAVEC = { 2366, 1}, + .XSAVEC64 = { 2367, 1}, + .XSAVES = { 2368, 1}, + .XSAVES64 = { 2369, 1}, + .XRSTORS = { 2370, 1}, + .XRSTORS64 = { 2371, 1}, + .PREFETCHT0 = { 2372, 1}, + .PREFETCHT1 = { 2373, 1}, + .PREFETCHT2 = { 2374, 1}, + .PREFETCHNTA = { 2375, 1}, + .PREFETCHW = { 2376, 1}, + .CLFLUSHOPT = { 2377, 1}, + .CLWB = { 2378, 1}, + .CLDEMOTE = { 2379, 1}, + .BSWAP = { 2380, 2}, + .CMPXCHG = { 2382, 4}, + .CMPXCHG8B = { 2386, 1}, + .CMPXCHG16B = { 2387, 1}, + .XADD = { 2388, 4}, + .BOUND = { 2392, 2}, + .ENTER = { 2394, 1}, + .LEAVE = { 2395, 1}, + .XLAT = { 2396, 1}, + .XLATB = { 2397, 1}, + .MOVBE = { 2398, 6}, + .RDRAND = { 2404, 3}, + .RDSEED = { 2407, 3}, + .SWAPGS = { 2410, 1}, + .MONITOR = { 2411, 1}, + .MWAIT = { 2412, 1}, + .CLAC = { 2413, 1}, + .STAC = { 2414, 1}, + .RDFSBASE = { 2415, 2}, + .RDGSBASE = { 2417, 2}, + .WRFSBASE = { 2419, 2}, + .WRGSBASE = { 2421, 2}, + .PTWRITE = { 2423, 2}, + .RDPID = { 2425, 1}, + .WBNOINVD = { 2426, 1}, + .SERIALIZE = { 2427, 1}, + .PREFETCH = { 2428, 1}, + .IN = { 2429, 6}, + .OUT = { 2435, 6}, + .TPAUSE = { 2441, 1}, + .UMONITOR = { 2442, 1}, + .UMWAIT = { 2443, 1}, + .MOVDIRI = { 2444, 2}, + .MOVDIR64B = { 2446, 1}, + .ENQCMD = { 2447, 1}, + .ENQCMDS = { 2448, 1}, + .AADD = { 2449, 2}, + .AAND = { 2451, 2}, + .AOR = { 2453, 2}, + .AXOR = { 2455, 2}, + .XEND = { 2457, 1}, + .XTEST = { 2458, 1}, + .VMRUN = { 2459, 1}, + .VMMCALL = { 2460, 1}, + .VMLOAD = { 2461, 1}, + .VMSAVE = { 2462, 1}, + .STGI = { 2463, 1}, + .CLGI = { 2464, 1}, + .SKINIT = { 2465, 1}, + .INVLPGA = { 2466, 1}, + .INVLPGB = { 2467, 1}, + .TLBSYNC = { 2468, 1}, + .PVALIDATE = { 2469, 1}, + .RMPADJUST = { 2470, 1}, + .RMPUPDATE = { 2471, 1}, + .PSMASH = { 2472, 1}, + .CLZERO = { 2473, 1}, + .MONITORX = { 2474, 1}, + .MWAITX = { 2475, 1}, + .RDPRU = { 2476, 1}, + .MCOMMIT = { 2477, 1}, } // Emit descriptor per form (derived from ENCODE_FORMS via lib.form_to_recipe). -ENCODE_RECIPES: [2466]lib.Form_Recipe +ENCODE_RECIPES: [2478]lib.Form_Recipe @(init) _fill_recipes :: proc "contextless" () { for i in 0 ..< len(ENCODE_FORMS) { ENCODE_RECIPES[i] = lib.form_to_recipe(&ENCODE_FORMS[i]) diff --git a/core/rexcode/isa/x86/tablegen/instruction_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin index 5288651d6..11e897138 100644 --- a/core/rexcode/isa/x86/tablegen/instruction_table.odin +++ b/core/rexcode/isa/x86/tablegen/instruction_table.odin @@ -462,6 +462,20 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, {{.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, + .SAL = { + {{.SAL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + }, .ROL = { {{.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, {{.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, diff --git a/core/rexcode/isa/x86/tables/x86.clobber_forms.bin b/core/rexcode/isa/x86/tables/x86.clobber_forms.bin index c0b69ba9d43a9ee43d0775aaf444fadb8ee66865..4bf6d0cd734d0fd52a99f6bfb711937eed0bd96c 100644 GIT binary patch delta 14 WcmZ3mh3UaorVVN$o704MwE+Mz8U{oF delta 14 WcmaE`m1)5irVVN$o1cmNY6So^Uk3yL diff --git a/core/rexcode/isa/x86/tables/x86.encode_forms.bin b/core/rexcode/isa/x86/tables/x86.encode_forms.bin index e82cda79057db3b5cc2e8b31b8aa3c01d055215a..a71e55be91b5c96de8a94254ec4bb1d13e17b881 100644 GIT binary patch literal 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z(PLEC%q*`}{r&Tjb(WS4w%^3xMRg_@1=~H*ZQ*O$#(6K;{{*%-&$gAb?mXxFz_tub d_w2jdS>rwYJ mnemonic_map; StringMap prefix_map; @@ -802,6 +802,18 @@ struct Asm_amd64 { } return true; } + AsmOperandConstraint operand_value_constraint(u16 m, int op) const { + switch (m) { + case M_SHL: case M_SHR: case M_SAR: case M_SAL: + case M_ROL: case M_ROR: case M_RCL: case M_RCR: + if (op == 1) return {AsmOperandConstraint_ShiftCount, /*width_operand*/0}; + break; + case M_DIV: case M_IDIV: + if (op == 0) return {AsmOperandConstraint_NonZeroDivisor, -1}; + break; + } + return {AsmOperandConstraint_None, -1}; + } }; @@ -812,83 +824,83 @@ gb_global Asm_amd64 g_asm_amd64; String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit(""), str_lit("mov"), str_lit("movabs"), str_lit("movzx"), str_lit("movsx"), str_lit("movsxd"), str_lit("xchg"), str_lit("push"), str_lit("pop"), str_lit("lea"), str_lit("add"), str_lit("adc"), str_lit("sub"), str_lit("sbb"), str_lit("mul"), str_lit("imul"), - str_lit("div"), str_lit("idiv"), str_lit("inc"), str_lit("dec"), str_lit("neg"), str_lit("cmp"), str_lit("and"), str_lit("or"), str_lit("xor"), str_lit("not"), str_lit("test"), str_lit("shl"), str_lit("shr"), str_lit("sar"), str_lit("rol"), str_lit("ror"), - str_lit("rcl"), str_lit("rcr"), str_lit("shld"), str_lit("shrd"), str_lit("bt"), str_lit("bts"), str_lit("btr"), str_lit("btc"), str_lit("bsf"), str_lit("bsr"), str_lit("popcnt"), str_lit("lzcnt"), str_lit("tzcnt"), str_lit("jmp"), str_lit("ja"), str_lit("jae"), - str_lit("jb"), str_lit("jbe"), str_lit("jc"), str_lit("je"), str_lit("jz"), str_lit("jg"), str_lit("jge"), str_lit("jl"), str_lit("jle"), str_lit("jna"), str_lit("jnae"), str_lit("jnb"), str_lit("jnbe"), str_lit("jnc"), str_lit("jne"), str_lit("jnz"), - str_lit("jng"), str_lit("jnge"), str_lit("jnl"), str_lit("jnle"), str_lit("jno"), str_lit("jnp"), str_lit("jns"), str_lit("jo"), str_lit("jp"), str_lit("jpe"), str_lit("jpo"), str_lit("js"), str_lit("jcxz"), str_lit("jecxz"), str_lit("jrcxz"), str_lit("loop"), - str_lit("loope"), str_lit("loopne"), str_lit("call"), str_lit("ret"), str_lit("iret"), str_lit("iretd"), str_lit("iretq"), str_lit("int"), str_lit("int3"), str_lit("into"), str_lit("syscall"), str_lit("sysret"), str_lit("sysenter"), str_lit("sysexit"), str_lit("seta"), str_lit("setae"), - str_lit("setb"), str_lit("setbe"), str_lit("setc"), str_lit("sete"), str_lit("setg"), str_lit("setge"), str_lit("setl"), str_lit("setle"), str_lit("setna"), str_lit("setnae"), str_lit("setnb"), str_lit("setnbe"), str_lit("setnc"), str_lit("setne"), str_lit("setng"), str_lit("setnge"), - str_lit("setnl"), str_lit("setnle"), str_lit("setno"), str_lit("setnp"), str_lit("setns"), str_lit("setnz"), str_lit("seto"), str_lit("setp"), str_lit("setpe"), str_lit("setpo"), str_lit("sets"), str_lit("setz"), str_lit("cmova"), str_lit("cmovae"), str_lit("cmovb"), str_lit("cmovbe"), - str_lit("cmovc"), str_lit("cmove"), str_lit("cmovg"), str_lit("cmovge"), str_lit("cmovl"), str_lit("cmovle"), str_lit("cmovna"), str_lit("cmovnae"), str_lit("cmovnb"), str_lit("cmovnbe"), str_lit("cmovnc"), str_lit("cmovne"), str_lit("cmovng"), str_lit("cmovnge"), str_lit("cmovnl"), str_lit("cmovnle"), - str_lit("cmovno"), str_lit("cmovnp"), str_lit("cmovns"), str_lit("cmovnz"), str_lit("cmovo"), str_lit("cmovp"), str_lit("cmovpe"), str_lit("cmovpo"), str_lit("cmovs"), str_lit("cmovz"), str_lit("movs"), str_lit("movsb"), str_lit("movsw"), str_lit("movsd"), str_lit("movsq"), str_lit("cmps"), - str_lit("cmpsb"), str_lit("cmpsw"), str_lit("cmpsd"), str_lit("cmpsq"), str_lit("scas"), str_lit("scasb"), str_lit("scasw"), str_lit("scasd"), str_lit("scasq"), str_lit("lods"), str_lit("lodsb"), str_lit("lodsw"), str_lit("lodsd"), str_lit("lodsq"), str_lit("stos"), str_lit("stosb"), - str_lit("stosw"), str_lit("stosd"), str_lit("stosq"), str_lit("clc"), str_lit("stc"), str_lit("cmc"), str_lit("cld"), str_lit("std"), str_lit("cli"), str_lit("sti"), str_lit("lahf"), str_lit("sahf"), str_lit("pushf"), str_lit("pushfd"), str_lit("pushfq"), str_lit("popf"), - str_lit("popfd"), str_lit("popfq"), str_lit("nop"), str_lit("hlt"), str_lit("wait"), str_lit("lock"), str_lit("ud0"), str_lit("ud1"), str_lit("ud2"), str_lit("cpuid"), str_lit("rdtsc"), str_lit("rdtscp"), str_lit("rdpmc"), str_lit("xgetbv"), str_lit("xsetbv"), str_lit("cbw"), - str_lit("cwde"), str_lit("cdqe"), str_lit("cwd"), str_lit("cdq"), str_lit("cqo"), str_lit("andn"), str_lit("bextr"), str_lit("blsi"), str_lit("blsmsk"), str_lit("blsr"), str_lit("bzhi"), str_lit("pdep"), str_lit("pext"), str_lit("rorx"), str_lit("sarx"), str_lit("shlx"), - str_lit("shrx"), str_lit("mulx"), str_lit("adcx"), str_lit("adox"), str_lit("movaps"), str_lit("movups"), str_lit("movapd"), str_lit("movupd"), str_lit("movss"), str_lit("movdqa"), str_lit("movdqu"), str_lit("movq"), str_lit("movd"), str_lit("movlps"), str_lit("movhps"), str_lit("movlpd"), - str_lit("movhpd"), str_lit("movlhps"), str_lit("movhlps"), str_lit("movmskps"), str_lit("movmskpd"), str_lit("movntps"), str_lit("movntpd"), str_lit("movntdq"), str_lit("movntdqa"), str_lit("addps"), str_lit("addpd"), str_lit("addss"), str_lit("addsd"), str_lit("subps"), str_lit("subpd"), str_lit("subss"), - str_lit("subsd"), str_lit("mulps"), str_lit("mulpd"), str_lit("mulss"), str_lit("mulsd"), str_lit("divps"), str_lit("divpd"), str_lit("divss"), str_lit("divsd"), str_lit("sqrtps"), str_lit("sqrtpd"), str_lit("sqrtss"), str_lit("sqrtsd"), str_lit("rcpps"), str_lit("rcpss"), str_lit("rsqrtps"), - str_lit("rsqrtss"), str_lit("maxps"), str_lit("maxpd"), str_lit("maxss"), str_lit("maxsd"), str_lit("minps"), str_lit("minpd"), str_lit("minss"), str_lit("minsd"), str_lit("andps"), str_lit("andpd"), str_lit("andnps"), str_lit("andnpd"), str_lit("orps"), str_lit("orpd"), str_lit("xorps"), - str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), str_lit("cvtps2pd"), str_lit("cvtpd2ps"), - str_lit("cvtss2sd"), str_lit("cvtsd2ss"), str_lit("cvtps2dq"), str_lit("cvtpd2dq"), str_lit("cvtdq2ps"), str_lit("cvtdq2pd"), str_lit("cvtss2si"), str_lit("cvtsd2si"), str_lit("cvtsi2ss"), str_lit("cvtsi2sd"), str_lit("cvttps2dq"), str_lit("cvttpd2dq"), str_lit("cvttss2si"), str_lit("cvttsd2si"), str_lit("paddb"), str_lit("paddw"), - str_lit("paddd"), str_lit("paddq"), str_lit("psubb"), str_lit("psubw"), str_lit("psubd"), str_lit("psubq"), str_lit("paddsb"), str_lit("paddsw"), str_lit("paddusb"), str_lit("paddusw"), str_lit("psubsb"), str_lit("psubsw"), str_lit("psubusb"), str_lit("psubusw"), str_lit("pmullw"), str_lit("pmulhw"), - str_lit("pmulhuw"), str_lit("pmuludq"), str_lit("pmaddwd"), str_lit("pand"), str_lit("pandn"), str_lit("por"), str_lit("pxor"), str_lit("psllw"), str_lit("pslld"), str_lit("psllq"), str_lit("psrlw"), str_lit("psrld"), str_lit("psrlq"), str_lit("psraw"), str_lit("psrad"), str_lit("pcmpeqb"), - str_lit("pcmpeqw"), str_lit("pcmpeqd"), str_lit("pcmpgtb"), str_lit("pcmpgtw"), str_lit("pcmpgtd"), str_lit("packsswb"), str_lit("packssdw"), str_lit("packuswb"), str_lit("punpcklbw"), str_lit("punpcklwd"), str_lit("punpckldq"), str_lit("punpcklqdq"), str_lit("punpckhbw"), str_lit("punpckhwd"), str_lit("punpckhdq"), str_lit("punpckhqdq"), - str_lit("pshufd"), str_lit("pshufhw"), str_lit("pshuflw"), str_lit("pshufw"), str_lit("pextrw"), str_lit("pinsrw"), str_lit("pmovmskb"), str_lit("pavgb"), str_lit("pavgw"), str_lit("pmaxub"), str_lit("pmaxsw"), str_lit("pminub"), str_lit("pminsw"), str_lit("psadbw"), str_lit("maskmovdqu"), str_lit("lfence"), - str_lit("sfence"), str_lit("mfence"), str_lit("pause"), str_lit("clflush"), str_lit("addsubps"), str_lit("addsubpd"), str_lit("haddps"), str_lit("haddpd"), str_lit("hsubps"), str_lit("hsubpd"), str_lit("movddup"), str_lit("movsldup"), str_lit("movshdup"), str_lit("lddqu"), str_lit("pshufb"), str_lit("phaddw"), - str_lit("phaddd"), str_lit("phaddsw"), str_lit("phsubw"), str_lit("phsubd"), str_lit("phsubsw"), str_lit("pmaddubsw"), str_lit("pmulhrsw"), str_lit("psignb"), str_lit("psignw"), str_lit("psignd"), str_lit("pabsb"), str_lit("pabsw"), str_lit("pabsd"), str_lit("palignr"), str_lit("blendps"), str_lit("blendpd"), - str_lit("blendvps"), str_lit("blendvpd"), str_lit("pblendw"), str_lit("pblendvb"), str_lit("dpps"), str_lit("dppd"), str_lit("extractps"), str_lit("insertps"), str_lit("mpsadbw"), str_lit("packusdw"), str_lit("pextrb"), str_lit("pextrd"), str_lit("pextrq"), str_lit("phminposuw"), str_lit("pinsrb"), str_lit("pinsrd"), - str_lit("pinsrq"), str_lit("pmaxsb"), str_lit("pmaxsd"), str_lit("pmaxuw"), str_lit("pmaxud"), str_lit("pminsb"), str_lit("pminsd"), str_lit("pminuw"), str_lit("pminud"), str_lit("pmovsxbw"), str_lit("pmovsxbd"), str_lit("pmovsxbq"), str_lit("pmovsxwd"), str_lit("pmovsxwq"), str_lit("pmovsxdq"), str_lit("pmovzxbw"), - str_lit("pmovzxbd"), str_lit("pmovzxbq"), str_lit("pmovzxwd"), str_lit("pmovzxwq"), str_lit("pmovzxdq"), str_lit("pmuldq"), str_lit("pmulld"), str_lit("ptest"), str_lit("roundps"), str_lit("roundpd"), str_lit("roundss"), str_lit("roundsd"), str_lit("pcmpeqq"), str_lit("crc32"), str_lit("pcmpestri"), str_lit("pcmpestrm"), - str_lit("pcmpistri"), str_lit("pcmpistrm"), str_lit("pcmpgtq"), str_lit("pclmulqdq"), str_lit("aesdec"), str_lit("aesdeclast"), str_lit("aesenc"), str_lit("aesenclast"), str_lit("aesimc"), str_lit("aeskeygenassist"), str_lit("sha1msg1"), str_lit("sha1msg2"), str_lit("sha1nexte"), str_lit("sha1rnds4"), str_lit("sha256msg1"), str_lit("sha256msg2"), - str_lit("sha256rnds2"), str_lit("vaddps"), str_lit("vaddpd"), str_lit("vaddss"), str_lit("vaddsd"), str_lit("vsubps"), str_lit("vsubpd"), str_lit("vsubss"), str_lit("vsubsd"), str_lit("vmulps"), str_lit("vmulpd"), str_lit("vmulss"), str_lit("vmulsd"), str_lit("vdivps"), str_lit("vdivpd"), str_lit("vdivss"), - str_lit("vdivsd"), str_lit("vsqrtps"), str_lit("vsqrtpd"), str_lit("vsqrtss"), str_lit("vsqrtsd"), str_lit("vrcpps"), str_lit("vrcpss"), str_lit("vrsqrtps"), str_lit("vrsqrtss"), str_lit("vmaxps"), str_lit("vmaxpd"), str_lit("vmaxss"), str_lit("vmaxsd"), str_lit("vminps"), str_lit("vminpd"), str_lit("vminss"), - str_lit("vminsd"), str_lit("vandps"), str_lit("vandpd"), str_lit("vandnps"), str_lit("vandnpd"), str_lit("vorps"), str_lit("vorpd"), str_lit("vxorps"), str_lit("vxorpd"), str_lit("vcmpps"), str_lit("vcmppd"), str_lit("vcmpss"), str_lit("vcmpsd"), str_lit("vcomiss"), str_lit("vcomisd"), str_lit("vucomiss"), - str_lit("vucomisd"), str_lit("vshufps"), str_lit("vshufpd"), str_lit("vunpcklps"), str_lit("vunpckhps"), str_lit("vunpcklpd"), str_lit("vunpckhpd"), str_lit("vblendps"), str_lit("vblendpd"), str_lit("vblendvps"), str_lit("vblendvpd"), str_lit("vdpps"), str_lit("vdppd"), str_lit("vroundps"), str_lit("vroundpd"), str_lit("vroundss"), - str_lit("vroundsd"), str_lit("vextractps"), str_lit("vinsertps"), str_lit("vmovaps"), str_lit("vmovups"), str_lit("vmovapd"), str_lit("vmovupd"), str_lit("vmovss"), str_lit("vmovsd"), str_lit("vmovdqa"), str_lit("vmovdqu"), str_lit("vmovq"), str_lit("vmovd"), str_lit("vmovlps"), str_lit("vmovhps"), str_lit("vmovlpd"), - str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vaddsubps"), str_lit("vaddsubpd"), str_lit("vhaddps"), str_lit("vhaddpd"), str_lit("vhsubps"), str_lit("vhsubpd"), str_lit("vlddqu"), - str_lit("vmovddup"), str_lit("vmovsldup"), str_lit("vmovshdup"), str_lit("vpcmpestri"), str_lit("vpcmpestrm"), str_lit("vpcmpistri"), str_lit("vpcmpistrm"), str_lit("vpbroadcastb"), str_lit("vpbroadcastw"), str_lit("vpbroadcastd"), str_lit("vpbroadcastq"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), str_lit("vcvtsd2ss"), str_lit("vcvtps2dq"), - str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), str_lit("vpaddq"), str_lit("vpsubb"), - str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), str_lit("vpsllq"), str_lit("vpsrlw"), - str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), str_lit("vpackuswb"), str_lit("vpackusdw"), - str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), str_lit("vpextrq"), str_lit("vpinsrb"), - str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), str_lit("vpsignb"), str_lit("vpsignw"), - str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), str_lit("vpminsd"), str_lit("vpminuw"), - str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), str_lit("vpmulld"), str_lit("vmaskmovdqu"), - str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), str_lit("vmaskmovpd"), str_lit("vtestps"), - str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), str_lit("vpsrlvd"), str_lit("vpsrlvq"), - str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), str_lit("vfmadd132pd"), str_lit("vfmadd213pd"), - str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), str_lit("vfmsub213ss"), str_lit("vfmsub231ss"), - str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), str_lit("vfnmadd231sd"), str_lit("vfnmsub132ps"), - str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), str_lit("vfmaddsub132pd"), str_lit("vfmaddsub213pd"), - str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), str_lit("vmovdqu64"), str_lit("vpblendmb"), - str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), str_lit("vptestmw"), str_lit("vptestmd"), - str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), str_lit("vpconflictq"), str_lit("vplzcntd"), - str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), str_lit("vpermw"), str_lit("vpmovb2m"), - str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), str_lit("vpmovsqd"), str_lit("vpmovusqd"), - str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), str_lit("vprorq"), str_lit("vprorvd"), - str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), str_lit("vrangepd"), str_lit("vrangess"), - str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), str_lit("vrcp14pd"), str_lit("vrcp14ss"), - str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), str_lit("vfixupimmpd"), str_lit("vfixupimmss"), - str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpdpwssd"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), str_lit("kaddd"), - str_lit("kandw"), str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), str_lit("knotd"), - str_lit("korw"), str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), str_lit("kshiftrd"), - str_lit("ktestw"), str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), str_lit("fadd"), - str_lit("faddp"), str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), str_lit("fdivrp"), - str_lit("fidivr"), str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), str_lit("fist"), - str_lit("fistp"), str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), str_lit("ficom"), - str_lit("ficomp"), str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), str_lit("fldln2"), - str_lit("fsin"), str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), str_lit("fwait"), - str_lit("fclex"), str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), str_lit("fxrstor"), - str_lit("fxrstor64"), str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), str_lit("verr"), - str_lit("verw"), str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), str_lit("vmptrst"), - str_lit("vmread"), str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), str_lit("rstorssp"), - str_lit("wrssd"), str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), str_lit("xsavec64"), - str_lit("xsaves"), str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), - str_lit("xadd"), str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), str_lit("swapgs"), str_lit("monitor"), str_lit("mwait"), str_lit("clac"), str_lit("stac"), str_lit("rdfsbase"), str_lit("rdgsbase"), - str_lit("wrfsbase"), str_lit("wrgsbase"), str_lit("ptwrite"), str_lit("rdpid"), str_lit("wbnoinvd"), str_lit("serialize"), str_lit("prefetch"), str_lit("in"), str_lit("out"), str_lit("tpause"), str_lit("umonitor"), str_lit("umwait"), str_lit("movdiri"), str_lit("movdir64b"), str_lit("enqcmd"), str_lit("enqcmds"), - str_lit("aadd"), str_lit("aand"), str_lit("aor"), str_lit("axor"), str_lit("xend"), str_lit("xtest"), str_lit("vmrun"), str_lit("vmmcall"), str_lit("vmload"), str_lit("vmsave"), str_lit("stgi"), str_lit("clgi"), str_lit("skinit"), str_lit("invlpga"), str_lit("invlpgb"), str_lit("tlbsync"), - str_lit("pvalidate"), str_lit("rmpadjust"), str_lit("rmpupdate"), str_lit("psmash"), str_lit("clzero"), str_lit("monitorx"), str_lit("mwaitx"), str_lit("rdpru"), str_lit("mcommit"), + str_lit("div"), str_lit("idiv"), str_lit("inc"), str_lit("dec"), str_lit("neg"), str_lit("cmp"), str_lit("and"), str_lit("or"), str_lit("xor"), str_lit("not"), str_lit("test"), str_lit("shl"), str_lit("shr"), str_lit("sar"), str_lit("sal"), str_lit("rol"), + str_lit("ror"), str_lit("rcl"), str_lit("rcr"), str_lit("shld"), str_lit("shrd"), str_lit("bt"), str_lit("bts"), str_lit("btr"), str_lit("btc"), str_lit("bsf"), str_lit("bsr"), str_lit("popcnt"), str_lit("lzcnt"), str_lit("tzcnt"), str_lit("jmp"), str_lit("ja"), + str_lit("jae"), str_lit("jb"), str_lit("jbe"), str_lit("jc"), str_lit("je"), str_lit("jz"), str_lit("jg"), str_lit("jge"), str_lit("jl"), str_lit("jle"), str_lit("jna"), str_lit("jnae"), str_lit("jnb"), str_lit("jnbe"), str_lit("jnc"), str_lit("jne"), + str_lit("jnz"), str_lit("jng"), str_lit("jnge"), str_lit("jnl"), str_lit("jnle"), str_lit("jno"), str_lit("jnp"), str_lit("jns"), str_lit("jo"), str_lit("jp"), str_lit("jpe"), str_lit("jpo"), str_lit("js"), str_lit("jcxz"), str_lit("jecxz"), str_lit("jrcxz"), + str_lit("loop"), str_lit("loope"), str_lit("loopne"), str_lit("call"), str_lit("ret"), str_lit("iret"), str_lit("iretd"), str_lit("iretq"), str_lit("int"), str_lit("int3"), str_lit("into"), str_lit("syscall"), str_lit("sysret"), str_lit("sysenter"), str_lit("sysexit"), str_lit("seta"), + str_lit("setae"), str_lit("setb"), str_lit("setbe"), str_lit("setc"), str_lit("sete"), str_lit("setg"), str_lit("setge"), str_lit("setl"), str_lit("setle"), str_lit("setna"), str_lit("setnae"), str_lit("setnb"), str_lit("setnbe"), str_lit("setnc"), str_lit("setne"), str_lit("setng"), + str_lit("setnge"), str_lit("setnl"), str_lit("setnle"), str_lit("setno"), str_lit("setnp"), str_lit("setns"), str_lit("setnz"), str_lit("seto"), str_lit("setp"), str_lit("setpe"), str_lit("setpo"), str_lit("sets"), str_lit("setz"), str_lit("cmova"), str_lit("cmovae"), str_lit("cmovb"), + str_lit("cmovbe"), str_lit("cmovc"), str_lit("cmove"), str_lit("cmovg"), str_lit("cmovge"), str_lit("cmovl"), str_lit("cmovle"), str_lit("cmovna"), str_lit("cmovnae"), str_lit("cmovnb"), str_lit("cmovnbe"), str_lit("cmovnc"), str_lit("cmovne"), str_lit("cmovng"), str_lit("cmovnge"), str_lit("cmovnl"), + str_lit("cmovnle"), str_lit("cmovno"), str_lit("cmovnp"), str_lit("cmovns"), str_lit("cmovnz"), str_lit("cmovo"), str_lit("cmovp"), str_lit("cmovpe"), str_lit("cmovpo"), str_lit("cmovs"), str_lit("cmovz"), str_lit("movs"), str_lit("movsb"), str_lit("movsw"), str_lit("movsd"), str_lit("movsq"), + str_lit("cmps"), str_lit("cmpsb"), str_lit("cmpsw"), str_lit("cmpsd"), str_lit("cmpsq"), str_lit("scas"), str_lit("scasb"), str_lit("scasw"), str_lit("scasd"), str_lit("scasq"), str_lit("lods"), str_lit("lodsb"), str_lit("lodsw"), str_lit("lodsd"), str_lit("lodsq"), str_lit("stos"), + str_lit("stosb"), str_lit("stosw"), str_lit("stosd"), str_lit("stosq"), str_lit("clc"), str_lit("stc"), str_lit("cmc"), str_lit("cld"), str_lit("std"), str_lit("cli"), str_lit("sti"), str_lit("lahf"), str_lit("sahf"), str_lit("pushf"), str_lit("pushfd"), str_lit("pushfq"), + str_lit("popf"), str_lit("popfd"), str_lit("popfq"), str_lit("nop"), str_lit("hlt"), str_lit("wait"), str_lit("lock"), str_lit("ud0"), str_lit("ud1"), str_lit("ud2"), str_lit("cpuid"), str_lit("rdtsc"), str_lit("rdtscp"), str_lit("rdpmc"), str_lit("xgetbv"), str_lit("xsetbv"), + str_lit("cbw"), str_lit("cwde"), str_lit("cdqe"), str_lit("cwd"), str_lit("cdq"), str_lit("cqo"), str_lit("andn"), str_lit("bextr"), str_lit("blsi"), str_lit("blsmsk"), str_lit("blsr"), str_lit("bzhi"), str_lit("pdep"), str_lit("pext"), str_lit("rorx"), str_lit("sarx"), + str_lit("shlx"), str_lit("shrx"), str_lit("mulx"), str_lit("adcx"), str_lit("adox"), str_lit("movaps"), str_lit("movups"), str_lit("movapd"), str_lit("movupd"), str_lit("movss"), str_lit("movdqa"), str_lit("movdqu"), str_lit("movq"), str_lit("movd"), str_lit("movlps"), str_lit("movhps"), + str_lit("movlpd"), str_lit("movhpd"), str_lit("movlhps"), str_lit("movhlps"), str_lit("movmskps"), str_lit("movmskpd"), str_lit("movntps"), str_lit("movntpd"), str_lit("movntdq"), str_lit("movntdqa"), str_lit("addps"), str_lit("addpd"), str_lit("addss"), str_lit("addsd"), str_lit("subps"), str_lit("subpd"), + str_lit("subss"), str_lit("subsd"), str_lit("mulps"), str_lit("mulpd"), str_lit("mulss"), str_lit("mulsd"), str_lit("divps"), str_lit("divpd"), str_lit("divss"), str_lit("divsd"), str_lit("sqrtps"), str_lit("sqrtpd"), str_lit("sqrtss"), str_lit("sqrtsd"), str_lit("rcpps"), str_lit("rcpss"), + str_lit("rsqrtps"), str_lit("rsqrtss"), str_lit("maxps"), str_lit("maxpd"), str_lit("maxss"), str_lit("maxsd"), str_lit("minps"), str_lit("minpd"), str_lit("minss"), str_lit("minsd"), str_lit("andps"), str_lit("andpd"), str_lit("andnps"), str_lit("andnpd"), str_lit("orps"), str_lit("orpd"), + str_lit("xorps"), str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), str_lit("cvtps2pd"), + str_lit("cvtpd2ps"), str_lit("cvtss2sd"), str_lit("cvtsd2ss"), str_lit("cvtps2dq"), str_lit("cvtpd2dq"), str_lit("cvtdq2ps"), str_lit("cvtdq2pd"), str_lit("cvtss2si"), str_lit("cvtsd2si"), str_lit("cvtsi2ss"), str_lit("cvtsi2sd"), str_lit("cvttps2dq"), str_lit("cvttpd2dq"), str_lit("cvttss2si"), str_lit("cvttsd2si"), str_lit("paddb"), + str_lit("paddw"), str_lit("paddd"), str_lit("paddq"), str_lit("psubb"), str_lit("psubw"), str_lit("psubd"), str_lit("psubq"), str_lit("paddsb"), str_lit("paddsw"), str_lit("paddusb"), str_lit("paddusw"), str_lit("psubsb"), str_lit("psubsw"), str_lit("psubusb"), str_lit("psubusw"), str_lit("pmullw"), + str_lit("pmulhw"), str_lit("pmulhuw"), str_lit("pmuludq"), str_lit("pmaddwd"), str_lit("pand"), str_lit("pandn"), str_lit("por"), str_lit("pxor"), str_lit("psllw"), str_lit("pslld"), str_lit("psllq"), str_lit("psrlw"), str_lit("psrld"), str_lit("psrlq"), str_lit("psraw"), str_lit("psrad"), + str_lit("pcmpeqb"), str_lit("pcmpeqw"), str_lit("pcmpeqd"), str_lit("pcmpgtb"), str_lit("pcmpgtw"), str_lit("pcmpgtd"), str_lit("packsswb"), str_lit("packssdw"), str_lit("packuswb"), str_lit("punpcklbw"), str_lit("punpcklwd"), str_lit("punpckldq"), str_lit("punpcklqdq"), str_lit("punpckhbw"), str_lit("punpckhwd"), str_lit("punpckhdq"), + str_lit("punpckhqdq"), str_lit("pshufd"), str_lit("pshufhw"), str_lit("pshuflw"), str_lit("pshufw"), str_lit("pextrw"), str_lit("pinsrw"), str_lit("pmovmskb"), str_lit("pavgb"), str_lit("pavgw"), str_lit("pmaxub"), str_lit("pmaxsw"), str_lit("pminub"), str_lit("pminsw"), str_lit("psadbw"), str_lit("maskmovdqu"), + str_lit("lfence"), str_lit("sfence"), str_lit("mfence"), str_lit("pause"), str_lit("clflush"), str_lit("addsubps"), str_lit("addsubpd"), str_lit("haddps"), str_lit("haddpd"), str_lit("hsubps"), str_lit("hsubpd"), str_lit("movddup"), str_lit("movsldup"), str_lit("movshdup"), str_lit("lddqu"), str_lit("pshufb"), + str_lit("phaddw"), str_lit("phaddd"), str_lit("phaddsw"), str_lit("phsubw"), str_lit("phsubd"), str_lit("phsubsw"), str_lit("pmaddubsw"), str_lit("pmulhrsw"), str_lit("psignb"), str_lit("psignw"), str_lit("psignd"), str_lit("pabsb"), str_lit("pabsw"), str_lit("pabsd"), str_lit("palignr"), str_lit("blendps"), + str_lit("blendpd"), str_lit("blendvps"), str_lit("blendvpd"), str_lit("pblendw"), str_lit("pblendvb"), str_lit("dpps"), str_lit("dppd"), str_lit("extractps"), str_lit("insertps"), str_lit("mpsadbw"), str_lit("packusdw"), str_lit("pextrb"), str_lit("pextrd"), str_lit("pextrq"), str_lit("phminposuw"), str_lit("pinsrb"), + str_lit("pinsrd"), str_lit("pinsrq"), str_lit("pmaxsb"), str_lit("pmaxsd"), str_lit("pmaxuw"), str_lit("pmaxud"), str_lit("pminsb"), str_lit("pminsd"), str_lit("pminuw"), str_lit("pminud"), str_lit("pmovsxbw"), str_lit("pmovsxbd"), str_lit("pmovsxbq"), str_lit("pmovsxwd"), str_lit("pmovsxwq"), str_lit("pmovsxdq"), + str_lit("pmovzxbw"), str_lit("pmovzxbd"), str_lit("pmovzxbq"), str_lit("pmovzxwd"), str_lit("pmovzxwq"), str_lit("pmovzxdq"), str_lit("pmuldq"), str_lit("pmulld"), str_lit("ptest"), str_lit("roundps"), str_lit("roundpd"), str_lit("roundss"), str_lit("roundsd"), str_lit("pcmpeqq"), str_lit("crc32"), str_lit("pcmpestri"), + str_lit("pcmpestrm"), str_lit("pcmpistri"), str_lit("pcmpistrm"), str_lit("pcmpgtq"), str_lit("pclmulqdq"), str_lit("aesdec"), str_lit("aesdeclast"), str_lit("aesenc"), str_lit("aesenclast"), str_lit("aesimc"), str_lit("aeskeygenassist"), str_lit("sha1msg1"), str_lit("sha1msg2"), str_lit("sha1nexte"), str_lit("sha1rnds4"), str_lit("sha256msg1"), + str_lit("sha256msg2"), str_lit("sha256rnds2"), str_lit("vaddps"), str_lit("vaddpd"), str_lit("vaddss"), str_lit("vaddsd"), str_lit("vsubps"), str_lit("vsubpd"), str_lit("vsubss"), str_lit("vsubsd"), str_lit("vmulps"), str_lit("vmulpd"), str_lit("vmulss"), str_lit("vmulsd"), str_lit("vdivps"), str_lit("vdivpd"), + str_lit("vdivss"), str_lit("vdivsd"), str_lit("vsqrtps"), str_lit("vsqrtpd"), str_lit("vsqrtss"), str_lit("vsqrtsd"), str_lit("vrcpps"), str_lit("vrcpss"), str_lit("vrsqrtps"), str_lit("vrsqrtss"), str_lit("vmaxps"), str_lit("vmaxpd"), str_lit("vmaxss"), str_lit("vmaxsd"), str_lit("vminps"), str_lit("vminpd"), + str_lit("vminss"), str_lit("vminsd"), str_lit("vandps"), str_lit("vandpd"), str_lit("vandnps"), str_lit("vandnpd"), str_lit("vorps"), str_lit("vorpd"), str_lit("vxorps"), str_lit("vxorpd"), str_lit("vcmpps"), str_lit("vcmppd"), str_lit("vcmpss"), str_lit("vcmpsd"), str_lit("vcomiss"), str_lit("vcomisd"), + str_lit("vucomiss"), str_lit("vucomisd"), str_lit("vshufps"), str_lit("vshufpd"), str_lit("vunpcklps"), str_lit("vunpckhps"), str_lit("vunpcklpd"), str_lit("vunpckhpd"), str_lit("vblendps"), str_lit("vblendpd"), str_lit("vblendvps"), str_lit("vblendvpd"), str_lit("vdpps"), str_lit("vdppd"), str_lit("vroundps"), str_lit("vroundpd"), + str_lit("vroundss"), str_lit("vroundsd"), str_lit("vextractps"), str_lit("vinsertps"), str_lit("vmovaps"), str_lit("vmovups"), str_lit("vmovapd"), str_lit("vmovupd"), str_lit("vmovss"), str_lit("vmovsd"), str_lit("vmovdqa"), str_lit("vmovdqu"), str_lit("vmovq"), str_lit("vmovd"), str_lit("vmovlps"), str_lit("vmovhps"), + str_lit("vmovlpd"), str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vaddsubps"), str_lit("vaddsubpd"), str_lit("vhaddps"), str_lit("vhaddpd"), str_lit("vhsubps"), str_lit("vhsubpd"), + str_lit("vlddqu"), str_lit("vmovddup"), str_lit("vmovsldup"), str_lit("vmovshdup"), str_lit("vpcmpestri"), str_lit("vpcmpestrm"), str_lit("vpcmpistri"), str_lit("vpcmpistrm"), str_lit("vpbroadcastb"), str_lit("vpbroadcastw"), str_lit("vpbroadcastd"), str_lit("vpbroadcastq"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), str_lit("vcvtsd2ss"), + str_lit("vcvtps2dq"), str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), str_lit("vpaddq"), + str_lit("vpsubb"), str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), str_lit("vpsllq"), + str_lit("vpsrlw"), str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), str_lit("vpackuswb"), + str_lit("vpackusdw"), str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), str_lit("vpextrq"), + str_lit("vpinsrb"), str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), str_lit("vpsignb"), + str_lit("vpsignw"), str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), str_lit("vpminsd"), + str_lit("vpminuw"), str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), str_lit("vpmulld"), + str_lit("vmaskmovdqu"), str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), str_lit("vmaskmovpd"), + str_lit("vtestps"), str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), str_lit("vpsrlvd"), + str_lit("vpsrlvq"), str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), str_lit("vfmadd132pd"), + str_lit("vfmadd213pd"), str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), str_lit("vfmsub213ss"), + str_lit("vfmsub231ss"), str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), str_lit("vfnmadd231sd"), + str_lit("vfnmsub132ps"), str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), str_lit("vfmaddsub132pd"), + str_lit("vfmaddsub213pd"), str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), str_lit("vmovdqu64"), + str_lit("vpblendmb"), str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), str_lit("vptestmw"), + str_lit("vptestmd"), str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), str_lit("vpconflictq"), + str_lit("vplzcntd"), str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), str_lit("vpermw"), + str_lit("vpmovb2m"), str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), str_lit("vpmovsqd"), + str_lit("vpmovusqd"), str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), str_lit("vprorq"), + str_lit("vprorvd"), str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), str_lit("vrangepd"), + str_lit("vrangess"), str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), str_lit("vrcp14pd"), + str_lit("vrcp14ss"), str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), str_lit("vfixupimmpd"), + str_lit("vfixupimmss"), str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpdpwssd"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), + str_lit("kaddd"), str_lit("kandw"), str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), + str_lit("knotd"), str_lit("korw"), str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), + str_lit("kshiftrd"), str_lit("ktestw"), str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), + str_lit("fadd"), str_lit("faddp"), str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), + str_lit("fdivrp"), str_lit("fidivr"), str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), + str_lit("fist"), str_lit("fistp"), str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), + str_lit("ficom"), str_lit("ficomp"), str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), + str_lit("fldln2"), str_lit("fsin"), str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), + str_lit("fwait"), str_lit("fclex"), str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), + str_lit("fxrstor"), str_lit("fxrstor64"), str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), + str_lit("verr"), str_lit("verw"), str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), + str_lit("vmptrst"), str_lit("vmread"), str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), + str_lit("rstorssp"), str_lit("wrssd"), str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), + str_lit("xsavec64"), str_lit("xsaves"), str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), + str_lit("cmpxchg16b"), str_lit("xadd"), str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), str_lit("swapgs"), str_lit("monitor"), str_lit("mwait"), str_lit("clac"), str_lit("stac"), str_lit("rdfsbase"), + str_lit("rdgsbase"), str_lit("wrfsbase"), str_lit("wrgsbase"), str_lit("ptwrite"), str_lit("rdpid"), str_lit("wbnoinvd"), str_lit("serialize"), str_lit("prefetch"), str_lit("in"), str_lit("out"), str_lit("tpause"), str_lit("umonitor"), str_lit("umwait"), str_lit("movdiri"), str_lit("movdir64b"), str_lit("enqcmd"), + str_lit("enqcmds"), str_lit("aadd"), str_lit("aand"), str_lit("aor"), str_lit("axor"), str_lit("xend"), str_lit("xtest"), str_lit("vmrun"), str_lit("vmmcall"), str_lit("vmload"), str_lit("vmsave"), str_lit("stgi"), str_lit("clgi"), str_lit("skinit"), str_lit("invlpga"), str_lit("invlpgb"), + str_lit("tlbsync"), str_lit("pvalidate"), str_lit("rmpadjust"), str_lit("rmpupdate"), str_lit("psmash"), str_lit("clzero"), str_lit("monitorx"), str_lit("mwaitx"), str_lit("rdpru"), str_lit("mcommit"), }; String const Asm_amd64::prefix_strings[Asm_amd64::PREFIX_COUNT] { str_lit(""), str_lit("es"), str_lit("cs"), str_lit("ss"), str_lit("ds"), str_lit("rex"), str_lit("evex"), str_lit("fs"), str_lit("gs"), str_lit("vex"), str_lit("lock"), str_lit("repne"), str_lit("rep"), @@ -926,87 +938,87 @@ String const Asm_amd64::register_strings[Asm_amd64::REG_COUNT] { str_lit("bnd2"), str_lit("bnd3"), str_lit("mm0"), str_lit("mm1"), str_lit("mm2"), str_lit("mm3"), str_lit("mm4"), str_lit("mm5"), str_lit("mm6"), str_lit("mm7"), str_lit("st0"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("st5"), str_lit("st6"), str_lit("st7"), str_lit("rip"), }; -Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1241] = { +Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1242] = { { 0, 0}, { 0, 32}, { 32, 9}, { 41, 5}, { 46, 5}, { 51, 1}, { 52, 7}, { 59, 9}, { 68, 6}, { 74, 3}, { 77, 19}, { 96, 19}, { 115, 19}, { 134, 19}, { 153, 4}, { 157, 13}, { 170, 4}, { 174, 4}, { 178, 6}, { 184, 6}, { 190, 4}, { 194, 19}, { 213, 19}, { 232, 19}, { 251, 19}, { 270, 4}, { 274, 12}, { 286, 12}, { 298, 12}, { 310, 12}, { 322, 12}, { 334, 12}, - { 346, 12}, { 358, 12}, { 370, 6}, { 376, 6}, { 382, 6}, { 388, 6}, { 394, 6}, { 400, 6}, { 406, 3}, { 409, 3}, { 412, 3}, { 415, 3}, { 418, 3}, { 421, 6}, { 427, 2}, { 429, 2}, - { 431, 2}, { 433, 2}, { 435, 2}, { 437, 2}, { 439, 2}, { 441, 2}, { 443, 2}, { 445, 2}, { 447, 2}, { 449, 2}, { 451, 2}, { 453, 2}, { 455, 2}, { 457, 2}, { 459, 2}, { 461, 2}, - { 463, 2}, { 465, 2}, { 467, 2}, { 469, 2}, { 471, 2}, { 473, 2}, { 475, 2}, { 477, 2}, { 479, 2}, { 481, 2}, { 483, 2}, { 485, 2}, { 487, 1}, { 488, 1}, { 489, 1}, { 490, 1}, - { 491, 1}, { 492, 1}, { 493, 5}, { 498, 2}, { 500, 1}, { 501, 1}, { 502, 1}, { 503, 1}, { 504, 1}, { 505, 1}, { 506, 1}, { 507, 1}, { 508, 1}, { 509, 1}, { 510, 1}, { 511, 1}, - { 512, 1}, { 513, 1}, { 514, 1}, { 515, 1}, { 516, 1}, { 517, 1}, { 518, 1}, { 519, 1}, { 520, 1}, { 521, 1}, { 522, 1}, { 523, 1}, { 524, 1}, { 525, 1}, { 526, 1}, { 527, 1}, - { 528, 1}, { 529, 1}, { 530, 1}, { 531, 1}, { 532, 1}, { 533, 1}, { 534, 1}, { 535, 1}, { 536, 1}, { 537, 1}, { 538, 1}, { 539, 1}, { 540, 3}, { 543, 3}, { 546, 3}, { 549, 3}, - { 552, 3}, { 555, 3}, { 558, 3}, { 561, 3}, { 564, 3}, { 567, 3}, { 570, 3}, { 573, 3}, { 576, 3}, { 579, 3}, { 582, 3}, { 585, 3}, { 588, 3}, { 591, 3}, { 594, 3}, { 597, 3}, - { 600, 3}, { 603, 3}, { 606, 3}, { 609, 3}, { 612, 3}, { 615, 3}, { 618, 3}, { 621, 3}, { 624, 3}, { 627, 3}, { 630, 1}, { 631, 1}, { 632, 1}, { 633, 3}, { 636, 1}, { 637, 1}, - { 638, 1}, { 639, 1}, { 640, 2}, { 642, 1}, { 643, 1}, { 644, 1}, { 645, 1}, { 646, 1}, { 647, 1}, { 648, 1}, { 649, 1}, { 650, 1}, { 651, 1}, { 652, 1}, { 653, 1}, { 654, 1}, - { 655, 1}, { 656, 1}, { 657, 1}, { 658, 1}, { 659, 1}, { 660, 1}, { 661, 1}, { 662, 1}, { 663, 1}, { 664, 1}, { 665, 1}, { 666, 1}, { 667, 1}, { 668, 1}, { 669, 1}, { 670, 1}, - { 671, 1}, { 672, 1}, { 673, 4}, { 677, 1}, { 678, 1}, { 679, 1}, { 680, 1}, { 681, 1}, { 682, 1}, { 683, 1}, { 684, 1}, { 685, 1}, { 686, 1}, { 687, 1}, { 688, 1}, { 689, 1}, - { 690, 1}, { 691, 1}, { 692, 1}, { 693, 1}, { 694, 1}, { 695, 2}, { 697, 2}, { 699, 2}, { 701, 2}, { 703, 2}, { 705, 2}, { 707, 2}, { 709, 2}, { 711, 2}, { 713, 2}, { 715, 2}, - { 717, 2}, { 719, 2}, { 721, 2}, { 723, 2}, { 725, 2}, { 727, 2}, { 729, 2}, { 731, 2}, { 733, 2}, { 735, 2}, { 737, 2}, { 739, 6}, { 745, 4}, { 749, 2}, { 751, 2}, { 753, 2}, - { 755, 2}, { 757, 1}, { 758, 1}, { 759, 2}, { 761, 2}, { 763, 1}, { 764, 1}, { 765, 1}, { 766, 1}, { 767, 1}, { 768, 1}, { 769, 1}, { 770, 1}, { 771, 1}, { 772, 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{ 705, 1}, { 706, 1}, { 707, 2}, { 709, 2}, { 711, 2}, { 713, 2}, { 715, 2}, { 717, 2}, { 719, 2}, { 721, 2}, { 723, 2}, { 725, 2}, + { 727, 2}, { 729, 2}, { 731, 2}, { 733, 2}, { 735, 2}, { 737, 2}, { 739, 2}, { 741, 2}, { 743, 2}, { 745, 2}, { 747, 2}, { 749, 2}, { 751, 6}, { 757, 4}, { 761, 2}, { 763, 2}, + { 765, 2}, { 767, 2}, { 769, 1}, { 770, 1}, { 771, 2}, { 773, 2}, { 775, 1}, { 776, 1}, { 777, 1}, { 778, 1}, { 779, 1}, { 780, 1}, { 781, 1}, { 782, 1}, { 783, 1}, { 784, 1}, + { 785, 1}, { 786, 1}, { 787, 1}, { 788, 1}, { 789, 1}, { 790, 1}, { 791, 1}, { 792, 1}, { 793, 1}, { 794, 1}, { 795, 1}, { 796, 1}, { 797, 1}, { 798, 1}, { 799, 1}, { 800, 1}, + { 801, 1}, { 802, 1}, { 803, 1}, { 804, 1}, { 805, 1}, { 806, 1}, { 807, 1}, { 808, 1}, { 809, 1}, { 810, 1}, { 811, 1}, { 812, 1}, { 813, 1}, { 814, 1}, { 815, 1}, { 816, 1}, + { 817, 1}, { 818, 1}, { 819, 1}, { 820, 1}, { 821, 1}, { 822, 1}, { 823, 1}, { 824, 1}, { 825, 1}, { 826, 1}, { 827, 1}, { 828, 1}, { 829, 1}, { 830, 1}, { 831, 1}, { 832, 1}, + { 833, 1}, { 834, 1}, { 835, 1}, { 836, 1}, { 837, 1}, { 838, 1}, { 839, 1}, { 840, 2}, { 842, 2}, { 844, 2}, { 846, 2}, { 848, 1}, { 849, 1}, { 850, 2}, { 852, 2}, { 854, 1}, + { 855, 1}, { 856, 1}, { 857, 1}, { 858, 1}, { 859, 1}, { 860, 1}, { 861, 1}, { 862, 1}, { 863, 1}, { 864, 1}, { 865, 1}, { 866, 1}, { 867, 1}, { 868, 1}, { 869, 1}, { 870, 1}, + { 871, 1}, { 872, 1}, { 873, 1}, { 874, 1}, { 875, 1}, { 876, 1}, { 877, 1}, { 878, 1}, { 879, 2}, { 881, 2}, { 883, 2}, { 885, 2}, { 887, 2}, { 889, 2}, { 891, 2}, { 893, 2}, + { 895, 1}, { 896, 1}, { 897, 1}, { 898, 1}, { 899, 1}, { 900, 1}, { 901, 1}, { 902, 1}, { 903, 1}, { 904, 1}, { 905, 1}, { 906, 1}, { 907, 1}, { 908, 1}, { 909, 1}, { 910, 1}, + { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 2}, { 918, 2}, { 920, 2}, { 922, 1}, { 923, 1}, { 924, 1}, { 925, 1}, { 926, 1}, { 927, 1}, { 928, 1}, { 929, 1}, + { 930, 1}, { 931, 1}, { 932, 1}, { 933, 1}, { 934, 1}, { 935, 1}, { 936, 1}, { 937, 1}, { 938, 1}, { 939, 1}, { 940, 1}, { 941, 1}, { 942, 1}, { 943, 1}, { 944, 1}, { 945, 1}, + { 946, 1}, { 947, 1}, { 948, 1}, { 949, 1}, { 950, 1}, { 951, 1}, { 952, 1}, { 953, 1}, { 954, 1}, { 955, 1}, { 956, 1}, { 957, 1}, { 958, 1}, { 959, 1}, { 960, 1}, { 961, 1}, + { 962, 1}, { 963, 1}, { 964, 1}, { 965, 1}, { 966, 1}, { 967, 1}, { 968, 1}, { 969, 1}, { 970, 1}, { 971, 1}, { 972, 1}, { 973, 1}, { 974, 1}, { 975, 1}, { 976, 1}, { 977, 1}, + { 978, 1}, { 979, 1}, { 980, 1}, { 981, 1}, { 982, 1}, { 983, 1}, { 984, 1}, { 985, 1}, { 986, 1}, { 987, 1}, { 988, 1}, { 989, 1}, { 990, 1}, { 991, 1}, { 992, 1}, { 993, 1}, + { 994, 1}, { 995, 1}, { 996, 1}, { 997, 1}, { 998, 1}, { 999, 1}, {1000, 1}, {1001, 1}, {1002, 1}, {1003, 1}, {1004, 1}, {1005, 1}, {1006, 1}, {1007, 1}, {1008, 5}, {1013, 1}, + {1014, 1}, {1015, 1}, {1016, 1}, {1017, 1}, {1018, 1}, {1019, 1}, {1020, 1}, {1021, 1}, {1022, 1}, {1023, 1}, {1024, 1}, {1025, 1}, {1026, 1}, {1027, 1}, {1028, 1}, {1029, 1}, + {1030, 1}, {1031, 1}, {1032, 2}, {1034, 2}, {1036, 1}, {1037, 1}, {1038, 2}, {1040, 2}, {1042, 1}, {1043, 1}, {1044, 2}, {1046, 2}, {1048, 1}, {1049, 1}, {1050, 2}, {1052, 2}, + {1054, 1}, {1055, 1}, {1056, 2}, {1058, 2}, {1060, 1}, {1061, 1}, {1062, 2}, {1064, 1}, {1065, 2}, {1067, 1}, {1068, 2}, {1070, 2}, {1072, 1}, {1073, 1}, {1074, 2}, {1076, 2}, + {1078, 1}, {1079, 1}, {1080, 2}, {1082, 2}, {1084, 2}, {1086, 2}, {1088, 2}, {1090, 2}, {1092, 2}, {1094, 2}, {1096, 2}, {1098, 2}, {1100, 1}, {1101, 1}, {1102, 1}, {1103, 1}, + {1104, 1}, {1105, 1}, {1106, 2}, {1108, 2}, {1110, 2}, {1112, 2}, {1114, 2}, {1116, 2}, {1118, 2}, {1120, 2}, {1122, 2}, {1124, 2}, {1126, 2}, {1128, 1}, {1129, 2}, {1131, 2}, + {1133, 1}, {1134, 1}, {1135, 1}, {1136, 1}, {1137, 4}, {1141, 4}, {1145, 4}, {1149, 4}, {1153, 3}, {1156, 3}, {1159, 4}, {1163, 4}, {1167, 4}, {1171, 2}, {1173, 2}, {1175, 2}, + {1177, 2}, {1179, 2}, {1181, 1}, {1182, 1}, {1183, 2}, {1185, 2}, {1187, 2}, {1189, 2}, {1191, 2}, {1193, 2}, {1195, 2}, {1197, 2}, {1199, 2}, {1201, 2}, {1203, 2}, {1205, 2}, + {1207, 2}, {1209, 2}, {1211, 2}, {1213, 2}, {1215, 1}, {1216, 1}, {1217, 1}, {1218, 1}, {1219, 4}, {1223, 4}, {1227, 4}, {1231, 4}, {1235, 2}, {1237, 2}, {1239, 1}, {1240, 1}, + {1241, 2}, {1243, 2}, {1245, 2}, {1247, 2}, {1249, 2}, {1251, 2}, {1253, 2}, {1255, 2}, {1257, 2}, {1259, 2}, {1261, 2}, {1263, 2}, {1265, 2}, {1267, 2}, {1269, 2}, {1271, 2}, + {1273, 2}, {1275, 2}, {1277, 2}, {1279, 2}, {1281, 2}, {1283, 2}, {1285, 2}, {1287, 2}, {1289, 2}, {1291, 2}, {1293, 2}, {1295, 2}, {1297, 2}, {1299, 4}, {1303, 4}, {1307, 4}, + {1311, 4}, {1315, 4}, {1319, 4}, {1323, 4}, {1327, 4}, {1331, 2}, {1333, 2}, {1335, 2}, {1337, 2}, {1339, 2}, {1341, 2}, {1343, 2}, {1345, 2}, {1347, 2}, {1349, 2}, {1351, 2}, + {1353, 2}, {1355, 2}, {1357, 2}, {1359, 2}, {1361, 2}, {1363, 2}, {1365, 2}, {1367, 2}, {1369, 2}, {1371, 2}, {1373, 2}, {1375, 2}, {1377, 1}, {1378, 2}, {1380, 1}, {1381, 1}, + {1382, 1}, {1383, 1}, {1384, 1}, {1385, 1}, {1386, 2}, {1388, 2}, {1390, 2}, {1392, 2}, {1394, 2}, {1396, 2}, {1398, 2}, {1400, 2}, {1402, 2}, {1404, 2}, {1406, 2}, {1408, 2}, + {1410, 2}, {1412, 2}, {1414, 2}, {1416, 2}, {1418, 2}, {1420, 2}, {1422, 2}, {1424, 2}, {1426, 2}, {1428, 1}, {1429, 2}, {1431, 2}, {1433, 2}, {1435, 2}, {1437, 2}, {1439, 2}, + {1441, 2}, {1443, 2}, {1445, 2}, {1447, 2}, {1449, 2}, {1451, 2}, {1453, 2}, {1455, 2}, {1457, 2}, {1459, 2}, {1461, 2}, {1463, 2}, {1465, 2}, {1467, 2}, {1469, 2}, {1471, 2}, + {1473, 1}, {1474, 2}, {1476, 1}, {1477, 1}, {1478, 1}, {1479, 1}, {1480, 1}, {1481, 1}, {1482, 4}, {1486, 2}, {1488, 1}, {1489, 1}, {1490, 1}, {1491, 1}, {1492, 4}, {1496, 4}, + {1500, 2}, {1502, 2}, {1504, 1}, {1505, 1}, {1506, 1}, {1507, 1}, {1508, 1}, {1509, 1}, {1510, 1}, {1511, 1}, {1512, 1}, {1513, 1}, {1514, 2}, {1516, 2}, {1518, 2}, {1520, 2}, + {1522, 2}, {1524, 2}, {1526, 4}, {1530, 4}, {1534, 2}, {1536, 2}, {1538, 2}, {1540, 2}, {1542, 2}, {1544, 2}, {1546, 2}, {1548, 2}, {1550, 2}, {1552, 2}, {1554, 2}, {1556, 2}, + {1558, 2}, {1560, 2}, {1562, 1}, {1563, 1}, {1564, 1}, {1565, 1}, {1566, 1}, {1567, 1}, {1568, 2}, {1570, 2}, {1572, 2}, {1574, 2}, {1576, 2}, {1578, 2}, {1580, 1}, {1581, 1}, + {1582, 1}, {1583, 1}, {1584, 1}, {1585, 1}, {1586, 2}, {1588, 2}, {1590, 2}, {1592, 2}, {1594, 2}, {1596, 2}, {1598, 1}, {1599, 1}, {1600, 1}, {1601, 1}, {1602, 1}, {1603, 1}, + {1604, 2}, {1606, 2}, {1608, 2}, {1610, 2}, {1612, 2}, {1614, 2}, {1616, 1}, {1617, 1}, {1618, 1}, {1619, 1}, {1620, 1}, {1621, 1}, {1622, 2}, {1624, 2}, {1626, 2}, {1628, 2}, + {1630, 2}, {1632, 2}, {1634, 2}, {1636, 2}, {1638, 2}, {1640, 2}, {1642, 2}, {1644, 2}, {1646, 3}, {1649, 3}, {1652, 6}, {1658, 6}, {1664, 6}, {1670, 6}, {1676, 6}, {1682, 6}, + {1688, 3}, {1691, 3}, {1694, 3}, {1697, 3}, {1700, 3}, {1703, 3}, {1706, 3}, {1709, 3}, {1712, 3}, {1715, 3}, {1718, 3}, {1721, 3}, {1724, 3}, {1727, 3}, {1730, 3}, {1733, 3}, + {1736, 3}, {1739, 3}, {1742, 3}, {1745, 3}, {1748, 3}, {1751, 3}, {1754, 3}, {1757, 3}, {1760, 3}, {1763, 3}, {1766, 3}, {1769, 3}, {1772, 3}, {1775, 3}, {1778, 3}, {1781, 3}, + {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 3}, {1814, 3}, {1817, 3}, {1820, 3}, {1823, 3}, {1826, 3}, {1829, 3}, + {1832, 3}, {1835, 3}, {1838, 3}, {1841, 3}, {1844, 3}, {1847, 3}, {1850, 3}, {1853, 3}, {1856, 3}, {1859, 3}, {1862, 3}, {1865, 3}, {1868, 3}, {1871, 3}, {1874, 3}, {1877, 3}, + {1880, 3}, {1883, 3}, {1886, 3}, {1889, 3}, {1892, 3}, {1895, 3}, {1898, 3}, {1901, 3}, {1904, 3}, {1907, 3}, {1910, 3}, {1913, 3}, {1916, 3}, {1919, 3}, {1922, 3}, {1925, 3}, + {1928, 3}, {1931, 3}, {1934, 3}, {1937, 3}, {1940, 3}, {1943, 3}, {1946, 3}, {1949, 3}, {1952, 3}, {1955, 3}, {1958, 3}, {1961, 3}, {1964, 3}, {1967, 3}, {1970, 3}, {1973, 3}, + {1976, 1}, {1977, 1}, {1978, 3}, {1981, 3}, {1984, 1}, {1985, 1}, {1986, 3}, {1989, 3}, {1992, 1}, {1993, 1}, {1994, 3}, {1997, 3}, {2000, 1}, {2001, 1}, {2002, 3}, {2005, 3}, + {2008, 1}, {2009, 1}, {2010, 3}, {2013, 3}, {2016, 1}, {2017, 1}, {2018, 3}, {2021, 3}, {2024, 1}, {2025, 1}, {2026, 3}, {2029, 3}, {2032, 1}, {2033, 1}, {2034, 3}, {2037, 3}, + {2040, 1}, {2041, 1}, {2042, 3}, {2045, 3}, {2048, 1}, {2049, 1}, {2050, 3}, {2053, 3}, {2056, 3}, {2059, 3}, {2062, 3}, {2065, 3}, {2068, 3}, {2071, 1}, {2072, 1}, {2073, 1}, + {2074, 1}, {2075, 1}, {2076, 1}, {2077, 1}, {2078, 1}, {2079, 1}, {2080, 1}, {2081, 1}, {2082, 1}, {2083, 4}, {2087, 4}, {2091, 4}, {2095, 4}, {2099, 1}, {2100, 1}, {2101, 1}, + {2102, 1}, {2103, 1}, {2104, 1}, {2105, 1}, {2106, 1}, {2107, 1}, {2108, 1}, {2109, 1}, {2110, 1}, {2111, 1}, {2112, 1}, {2113, 1}, {2114, 1}, {2115, 1}, {2116, 1}, {2117, 1}, + {2118, 1}, {2119, 1}, {2120, 1}, {2121, 1}, {2122, 1}, {2123, 1}, {2124, 1}, {2125, 1}, {2126, 1}, {2127, 1}, {2128, 1}, {2129, 1}, {2130, 1}, {2131, 1}, {2132, 1}, {2133, 1}, + {2134, 4}, {2138, 2}, {2140, 2}, {2142, 4}, {2146, 2}, {2148, 2}, {2150, 4}, {2154, 2}, {2156, 2}, {2158, 4}, {2162, 2}, {2164, 2}, {2166, 4}, {2170, 2}, {2172, 2}, {2174, 4}, + {2178, 2}, {2180, 2}, {2182, 1}, {2183, 1}, {2184, 1}, {2185, 1}, {2186, 1}, {2187, 1}, {2188, 1}, {2189, 1}, {2190, 1}, {2191, 4}, {2195, 3}, {2198, 1}, {2199, 3}, {2202, 4}, + {2206, 2}, {2208, 3}, {2211, 3}, {2214, 1}, {2215, 2}, {2217, 1}, {2218, 1}, {2219, 1}, {2220, 1}, {2221, 1}, {2222, 1}, {2223, 1}, {2224, 1}, {2225, 4}, {2229, 4}, {2233, 1}, + {2234, 2}, {2236, 2}, {2238, 1}, {2239, 1}, {2240, 1}, {2241, 1}, {2242, 2}, {2244, 2}, {2246, 1}, {2247, 1}, {2248, 1}, {2249, 1}, {2250, 1}, {2251, 1}, {2252, 1}, {2253, 1}, + {2254, 1}, {2255, 1}, {2256, 1}, {2257, 1}, {2258, 1}, {2259, 1}, {2260, 1}, {2261, 1}, {2262, 1}, {2263, 1}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 1}, {2268, 1}, {2269, 1}, + {2270, 1}, {2271, 1}, {2272, 1}, {2273, 1}, {2274, 1}, {2275, 1}, {2276, 1}, {2277, 1}, {2278, 1}, {2279, 1}, {2280, 1}, {2281, 1}, {2282, 2}, {2284, 2}, {2286, 1}, {2287, 1}, + {2288, 1}, {2289, 1}, {2290, 2}, {2292, 2}, {2294, 2}, {2296, 2}, {2298, 1}, {2299, 3}, {2302, 1}, {2303, 3}, {2306, 1}, {2307, 3}, {2310, 1}, {2311, 1}, {2312, 3}, {2315, 3}, + {2318, 1}, {2319, 1}, {2320, 1}, {2321, 1}, {2322, 1}, {2323, 2}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, + {2335, 1}, {2336, 1}, {2337, 1}, {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, + {2351, 1}, {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 1}, {2366, 1}, + {2367, 1}, {2368, 1}, {2369, 1}, {2370, 1}, {2371, 1}, {2372, 1}, {2373, 1}, {2374, 1}, {2375, 1}, {2376, 1}, {2377, 1}, {2378, 1}, {2379, 1}, {2380, 2}, {2382, 4}, {2386, 1}, + {2387, 1}, {2388, 4}, {2392, 2}, {2394, 1}, {2395, 1}, {2396, 1}, {2397, 1}, {2398, 6}, {2404, 3}, {2407, 3}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 2}, + {2417, 2}, {2419, 2}, {2421, 2}, {2423, 2}, {2425, 1}, {2426, 1}, {2427, 1}, {2428, 1}, {2429, 6}, {2435, 6}, {2441, 1}, {2442, 1}, {2443, 1}, {2444, 2}, {2446, 1}, {2447, 1}, + {2448, 1}, {2449, 2}, {2451, 2}, {2453, 2}, {2455, 2}, {2457, 1}, {2458, 1}, {2459, 1}, {2460, 1}, {2461, 1}, {2462, 1}, {2463, 1}, {2464, 1}, {2465, 1}, {2466, 1}, {2467, 1}, + {2468, 1}, {2469, 1}, {2470, 1}, {2471, 1}, {2472, 1}, {2473, 1}, {2474, 1}, {2475, 1}, {2476, 1}, {2477, 1}, }; -u8 const Asm_amd64::raw_encode_forms[39456] = { +u8 const Asm_amd64::raw_encode_forms[39648] = { 0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x06, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x07, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x00, 0x01, 0x05, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x00, 0x01, 0x12, 0x00, 0x00, 0x04, 0x05, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x13, 0x00, 0x00, 0x04, 0x06, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x14, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x15, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x08, 0x08, 0x00, @@ -1087,545 +1099,548 @@ u8 const Asm_amd64::raw_encode_forms[39456] = { 0x1c, 0x00, 0x08, 0x1d, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0xd3, 0x05, 0x00, 0x08, 0x25, 0x00, 0x1c, 0x00, 0x08, 0x12, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0xc1, 0x05, 0x00, 0x08, 0x09, 0x00, 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0x00, 0x00, 0x00, 0xcd, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xde, 0x01, 0x00, 0x00, 0x00, 0xce, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf, 0x01, 0x00, 0x00, 0x00, 0xcf, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x01, 0x00, 0x00, 0x00, + 0xd0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x01, 0x00, 0x00, 0x00, 0xd1, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x0d, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x09, 0x00, 0x00, 0x00, 0xd3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x0d, 0x00, 0x00, 0x00, + 0xd4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x09, 0x00, 0x00, 0x00, 0xd5, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfc, 0x01, 0x00, 0x00, 0x00, 0xd6, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x01, 0x00, 0x00, 0x00, 0xd7, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfb, 0x01, 0x00, 0x00, 0x00, + 0xd8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfd, 0x01, 0x00, 0x00, 0x00, 0xd9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x09, 0x00, 0x00, 0x00, }; -u8 const Asm_amd64::raw_clobber_forms[39456] = { +u8 const Asm_amd64::raw_clobber_forms[39648] = { 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1706,6 +1721,9 @@ u8 const Asm_amd64::raw_clobber_forms[39456] = { 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x04, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, diff --git a/src/asm_tables_riscv.cpp b/src/asm_tables_riscv.cpp index 2ffdadd58..85714c37e 100644 --- a/src/asm_tables_riscv.cpp +++ b/src/asm_tables_riscv.cpp @@ -745,6 +745,17 @@ struct Asm_riscv { // RISC-V does not have prefixes return false; } + AsmOperandConstraint operand_value_constraint(u16 m, int op) const { + switch (m) { + case M_SLLI: case M_SRLI: case M_SRAI: + if (op == 2) return {AsmOperandConstraint_ShiftCount, /*XLEN*/-1}; + break; + case M_DIV: case M_DIVU: case M_REM: case M_REMU: + if (op == 2) return {AsmOperandConstraint_NonZeroDivisor, -1}; + break; + } + return {AsmOperandConstraint_None, -1}; + } }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 7f5a5ab0a..fe06cfe51 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -107,7 +107,7 @@ gb_internal void check_asm_pin_type_compat(AsmRegClass reg_class, i32 reg_w, Typ AsmRegClass got_class = check_asm_reg_class_from_type(decl_type); i32 got_w = check_asm_operand_bit_width(decl_type); - if (!!asm_reg_class_compatible(reg_class, got_class)) { + if (!asm_reg_class_compatible(reg_class, got_class)) { error(at, "Parameter '%.*s' is pinned to %%%.*s, but its type is in the wrong register class for that register", LIT(param_name), LIT(pin_name)); return; @@ -575,7 +575,7 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc if (pin.len != 0) { Operand op = {}; if (check_register(asm_ctx, &op, reg)) { - if (reg->flag.string.len) { + if (reg->flag.string.len != 0) { GB_ASSERT(pin == "flags"); pin_flag = reg->flag.string; if (string_set_update(&pin_flag_set, pin_flag)) { @@ -1063,6 +1063,57 @@ gb_internal bool check_asm_instr_targets_internal_label(AstAsmInstruction *instr } +template +gb_internal void check_operand_constraints(AsmCtx *asm_ctx, Slice const &operands, u16 mnemonic, String const &name) { + i32 word_bits = cast(i32)(build_context.metrics.ptr_size * 8); + + // Value-range constraints (shift-count in range, non-zero divisor). Every mnemonic + // decision lives in asm_ctx->operand_value_constraint; the logic below names none. + for_array(i, operands) { + Operand const *op = &operands[i]; + if (op->mode != Addressing_Constant) { + continue; // register count (cl/rs2) or $-immediate: not knowable here + } + ExactValue ev = exact_value_to_integer(op->value); + if (ev.kind != ExactValue_Integer) { + continue; + } + + AsmOperandConstraint c = asm_ctx->operand_value_constraint(mnemonic, cast(int)i); + switch (c.kind) { + case AsmOperandConstraint_ShiftCount: { + i32 width = 0; + if (c.width_operand < 0) { + width = word_bits; + } else if (c.width_operand < operands.count) { + width = check_asm_operand_bit_width(operands[c.width_operand].type); + } + if (width <= 0) { + break; // unknown target width; nothing to compare against + } + mp_int const *v = &ev.value_integer; + bool too_big = mp_count_bits(v) > 63; + i64 count = too_big ? 0 : exact_value_to_i64(ev); + if (mp_isneg(v) || too_big || count >= width) { + gbString vs = exact_value_to_string(ev); + error(op->expr, "'%.*s' shift count %s is out of range for a %d-bit operand (must be 0..<%d)", + LIT(name), vs, cast(int)width, cast(int)width); + gb_string_free(vs); + } + } break; + + case AsmOperandConstraint_NonZeroDivisor: + if (mp_iszero(&ev.value_integer)) { + error(op->expr, "'%.*s' divides by a constant zero", LIT(name)); + } + break; + + case AsmOperandConstraint_None: + break; + } + } +} + template gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, u16 mnemonic, u16 pseudo_mnemonic, Slice const &operands, @@ -1470,6 +1521,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm instr->mnemonic = mnemonic; instr->valid_form_index = cast(i32)valid_form_index; + check_operand_constraints(asm_ctx, operands, mnemonic, name); + // Handle clobbering from mnemonic auto clobber = clobber_forms[valid_form_index]; @@ -2705,6 +2758,11 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity continue; } } + if (ed.tie > 0) { + // TODO(bill): Handle this edge case + continue; + } + char const *what = is_immediate ? "immediate" : is_input ? "input" : "scratch"; From dfa473f2c86a2690ce40e6ecea14d7bbe6eff69b Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 18:20:12 +0100 Subject: [PATCH 28/54] Minor grammar fix in error message --- src/check_asm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index fe06cfe51..98ab7fc49 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1096,7 +1096,7 @@ gb_internal void check_operand_constraints(AsmCtx *asm_ctx, Slice const i64 count = too_big ? 0 : exact_value_to_i64(ev); if (mp_isneg(v) || too_big || count >= width) { gbString vs = exact_value_to_string(ev); - error(op->expr, "'%.*s' shift count %s is out of range for a %d-bit operand (must be 0..<%d)", + error(op->expr, "'%.*s' shift count %s is out of range for the %d-bit operand (must be 0..<%d)", LIT(name), vs, cast(int)width, cast(int)width); gb_string_free(vs); } From 3e159a4e10918f9feddae89c15cf49706f610bd8 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 19:10:32 +0100 Subject: [PATCH 29/54] Add `#no_init` suffix directive for asm specifications. --- src/check_asm.cpp | 26 +++++++++++++ src/entity.cpp | 2 + src/parser.cpp | 99 ++++++++++++++++++++++++++++------------------- src/parser.hpp | 9 +++-- 4 files changed, 93 insertions(+), 43 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 98ab7fc49..f8fa94d0f 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -793,6 +793,26 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc error(spec->value, "Input parameters, and thus tied parameters, cannot be pinned to a flag style register"); } } + + + for (Ast *dir_ : spec->directives) { + ast_node(dir, BasicDirective, dir_); + String name = dir->name.string; + if (name == "no_init") { + i32 input_index = -1; + check_asm_find_group(input, *asm_template_entity_decls, &input_index); + if (input_index >= 0) { + auto *i = &(*asm_template_entity_decls)[input_index]; + i->no_init = true; + if (i->tie >= 0) { + auto *o = &(*asm_template_entity_decls)[i->tie]; + o->no_init = true; + } + } + } else { + error(dir_, "Invalid directive for an asm specification, got '#%.*s'", LIT(name)); + } + } } } @@ -2451,6 +2471,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity // straight-line instruction stream. Seeded with input-pinned registers (they // carry their argument at entry); grows as instructions write registers. for (auto const &ed : ate->decls) { + if (ed.no_init) { + ptr_set_add(&asm_acc.defined_params, ed.entity); + } switch (ed.param_group) { case AsmTemplateEntityDeclParamGroup_Input: if (ed.pin.len != 0) { @@ -2683,6 +2706,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity if (ed.tie >= 0) { continue; } + if (ed.no_init) { + continue; + } if (!asm_acc.straight_line) { continue; } diff --git a/src/entity.cpp b/src/entity.cpp index f6045e341..b70f09045 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -196,6 +196,8 @@ struct AsmTemplateEntityDecl { i32 view_of; // total_index of the source operand this is a width-view of, else -1 i32 view_bits; // the view width in bits, otherwise 0 + + bool no_init; }; // An Entity is a named "thing" in the language diff --git a/src/parser.cpp b/src/parser.cpp index 1173305f8..f8ccb79a6 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -533,10 +533,11 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { case Ast_AsmRegister: break; case Ast_AsmSpec: - n->AsmSpec.name = clone_ast(n->AsmSpec.name, f); - n->AsmSpec.tied_name = clone_ast(n->AsmSpec.tied_name, f); - n->AsmSpec.type = clone_ast(n->AsmSpec.type, f); - n->AsmSpec.value = clone_ast(n->AsmSpec.value, f); + n->AsmSpec.name = clone_ast(n->AsmSpec.name, f); + n->AsmSpec.tied_name = clone_ast(n->AsmSpec.tied_name, f); + n->AsmSpec.type = clone_ast(n->AsmSpec.type, f); + n->AsmSpec.value = clone_ast(n->AsmSpec.value, f); + n->AsmSpec.directives = clone_ast_array(n->AsmSpec.directives, f); break; case Ast_AsmClobber: n->AsmClobber.value = clone_ast(n->AsmClobber.value, f); @@ -2694,6 +2695,60 @@ gb_internal Ast *parse_asm_signature(AstFile *f, Token asm_token) { return ast_proc_type(f, asm_token, params, results, tags, cc, is_generic, diverging); } +gb_internal Ast *parse_asm_spec(AstFile *f) { + Ast *name = parse_ident(f); + Ast *tied_name = nullptr; + Ast *type = nullptr; + Ast *value = nullptr; + if (allow_token(f, Token_ArrowRight)) { + tied_name = parse_ident(f); + } + if (allow_token(f, Token_Colon)) { + type = parse_type(f); + } + if (allow_token(f, Token_Eq)) { + if (f->curr_token.kind == Token_Ident) { + value = parse_ident(f); + } else if (f->curr_token.kind == Token_Mod) { + value = parse_asm_register(f); + } else { + error(f->curr_token, "Expected a register or scratch parameter"); + Ast *dummy = parse_expr(f, true); + gb_unused(dummy); + } + } + + if (tied_name != nullptr) { + if (type != nullptr) { + syntax_error(f->curr_token, "An asm specification for tied values cannot declare a type"); + } + } else if (type == nullptr && value == nullptr) { + syntax_error(f->curr_token, "An asm specification must specify at least either a type or a value if the value is not tied"); + } + + Array directives = {}; + directives.allocator = heap_allocator(); + + while (f->curr_token.kind == Token_Hash) { + Token token = expect_token(f, Token_Hash); + Token name = expect_token_after(f, Token_Ident, "hash for directive"); + if (name.kind == Token_Ident) { + Ast *directive = ast_basic_directive(f, token, name); + array_add(&directives, directive); + } + } + + + Ast *spec = alloc_ast_node(f, Ast_AsmSpec); + spec->AsmSpec.name = name; + spec->AsmSpec.tied_name = tied_name; + spec->AsmSpec.type = type; + spec->AsmSpec.value = value; + spec->AsmSpec.directives = directives; + return spec; +} + + gb_internal Ast *parse_asm_template(AstFile *f) { Token token = expect_token(f, Token_asm); @@ -2718,41 +2773,7 @@ gb_internal Ast *parse_asm_template(AstFile *f) { f->curr_token.kind != Token_EOF) { Ast *spec = nullptr; if (f->curr_token.kind == Token_Ident) { - Ast *name = parse_ident(f); - Ast *tied_name = nullptr; - Ast *type = nullptr; - Ast *value = nullptr; - if (allow_token(f, Token_ArrowRight)) { - tied_name = parse_ident(f); - } - if (allow_token(f, Token_Colon)) { - type = parse_type(f); - } - if (allow_token(f, Token_Eq)) { - if (f->curr_token.kind == Token_Ident) { - value = parse_ident(f); - } else if (f->curr_token.kind == Token_Mod) { - value = parse_asm_register(f); - } else { - error(f->curr_token, "Expected a register or scratch parameter"); - Ast *dummy = parse_expr(f, true); - gb_unused(dummy); - } - } - - if (tied_name != nullptr) { - if (type != nullptr) { - syntax_error(f->curr_token, "An asm specification for tied values cannot declare a type"); - } - } else if (type == nullptr && value == nullptr) { - syntax_error(f->curr_token, "An asm specification must specify at least either a type or a value if the value is not tied"); - } - - spec = alloc_ast_node(f, Ast_AsmSpec); - spec->AsmSpec.name = name; - spec->AsmSpec.tied_name = tied_name; - spec->AsmSpec.type = type; - spec->AsmSpec.value = value; + spec = parse_asm_spec(f); } else if (f->curr_token.kind == Token_Hash) { Token hash = expect_token(f, Token_Hash); Token name = expect_token(f, Token_Ident); diff --git a/src/parser.hpp b/src/parser.hpp index efc8be219..ad82834ed 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -489,10 +489,11 @@ struct AstSplitArgs { Token flag; \ }) \ AST_KIND(AsmSpec, "asm specification", struct { \ - Ast *name; \ - Ast *tied_name; \ - Ast *type; \ - Ast *value; \ + Ast * name; \ + Ast * tied_name; \ + Ast * type; \ + Ast * value; \ + Array directives; \ }) \ AST_KIND(AsmClobber, "asm clobber", struct { \ Token token; \ From b69e61983a93f492259337a30d4c1053a81865dd Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 19:52:56 +0100 Subject: [PATCH 30/54] Mock out the data structures for working on a CFG for `asm` --- src/check_asm.cpp | 145 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 113 insertions(+), 32 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index f8fa94d0f..1f2517210 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1,3 +1,64 @@ +struct AsmBlock { + i32 first, last; + Array succs; + u16 in_defs; + u16 out_defs; + PtrSet in_params; + PtrSet out_params; + bool reachable; +}; + +struct AsmInstructionFacts { + AstAsmInstruction *node; + String name; + + u16 gen_regs; + u16 read_regs; + + Array gen_params; + Array read_params; + + bool is_control; + bool is_conditional; + bool is_terminal; + + Entity *branch_target; + i32 block_id; +}; + + +struct AsmMnemonicAccumulator { + u16 defined_regs; + PtrSet defined_params; + + // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). + u16 implicit_clobbered_regs; + u16 explicitly_produced_regs; + u16 stale_outputs; + + bool straight_line; + + // Whether the most-recently-checked instruction terminates straight-line flow. + // Reset to false at every label (a label starts a fresh straight-line region whose + // tail we haven't seen yet). Consulted after the loop for #diverging templates. + bool last_is_terminal; + + // Did the template contain any instructions at all? An empty diverging body can't diverge. + bool saw_any_instructions; + + // Related to #align_stack + // any call/branch (CONTROL) or memory effect that could require the stack + // to be realigned. If none occurred, #align_stack is redundant. + bool saw_call_or_mem; + + // Purity test + bool can_be_pure; + char const *impure_reason; + Ast * impure_reason_node; + + PtrMap instruction_facts; +}; + // Bit-width the operand's Odin type occupies in a register/immediate slot. // Integers/floats/bools/pointers -> their size; #simd -> total vector width. 0 if unknown. gb_internal i32 check_asm_operand_bit_width(Type *type) { @@ -1042,36 +1103,6 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AsmCtx *asm_ctx, AstAsmInstr return CheckMnemomic_Invalid; } -struct AsmMnemonicAccumulator { - u16 defined_regs; - PtrSet defined_params; - - // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). - u16 implicit_clobbered_regs; - u16 explicitly_produced_regs; - u16 stale_outputs; - - bool straight_line; - - // Whether the most-recently-checked instruction terminates straight-line flow. - // Reset to false at every label (a label starts a fresh straight-line region whose - // tail we haven't seen yet). Consulted after the loop for #diverging templates. - bool last_is_terminal; - - // Did the template contain any instructions at all? An empty diverging body can't diverge. - bool saw_any_instructions; - - // Related to #align_stack - // any call/branch (CONTROL) or memory effect that could require the stack - // to be realigned. If none occurred, #align_stack is redundant. - bool saw_call_or_mem; - - // Purity test - bool can_be_pure; - char const *impure_reason; - Ast * impure_reason_node; -}; - gb_internal bool check_asm_instr_targets_internal_label(AstAsmInstruction *instr) { bool saw_label = false; for (Ast *op : instr->operands) { @@ -1149,6 +1180,29 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm name = asm_ctx->pseudo_mnemonic_strings[pseudo_mnemonic]; } + AsmInstructionFacts facts = {}; + facts.node = instr; + facts.name = name; + facts.gen_params.allocator = heap_allocator(); + facts.read_params.allocator = heap_allocator(); + + defer ({ + for (auto const &op : operands) { + if (op.expr->kind != Ast_AsmLabelDecl) { + continue; + } + Entity *e = op.expr->AsmLabelDecl.name->Ident.entity; + if (e == nullptr || e->kind != Entity_Label) { + continue; + } + facts.branch_target = e; + break; + } + + map_set(&asm_acc->instruction_facts, instr, facts); + }); + + bool is_pseudo = pseudo_mnemonic != 0; int target_explicit_count = is_pseudo ? alias.nargs : -1; @@ -1546,6 +1600,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // Handle clobbering from mnemonic auto clobber = clobber_forms[valid_form_index]; + facts.read_regs = cast(u16)clobber.implicit_rd & asm_ctx->CLOBBER_REGS_NAMED; + // NOTE(bill): reads_mem/writes_mem are per-FORM capability bits. // A form with an r/m slot (e.g. add r/m32, imm32) carries them even // when the operand resolved to a register, e.g. `add x, 123`. @@ -1704,7 +1760,26 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm produced |= synth; explicit_writes |= synth; } - asm_acc->defined_regs |= produced | pinned_param_writes; + + facts.gen_regs = produced | pinned_param_writes; + asm_acc->defined_regs |= facts.gen_regs; + + for_array(i, operands) { + int slot = user_operand_target_index(cast(int)i); + if (slot < 0) { + continue; + } + Entity *pe = entity_of_node(operands[i].expr); + if (pe == nullptr || pe->kind != Entity_Variable) { + continue; + } + if (cast(u16)clobber.read & (1u << slot)) { + array_add(&facts.read_params, pe); + } + if (cast(u16)clobber.written & (1u << slot)) { + array_add(&facts.gen_params, pe); + } + } if (asm_acc->straight_line) { // NOTE(bill): check for read-before-write (use of undefined value) @@ -1769,6 +1844,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm bool conditional = clobber.is_conditional(); asm_acc->last_is_terminal = halt || (control && !conditional); + facts.is_control = control; + facts.is_conditional = conditional; + facts.is_terminal = halt || (control && !conditional); + if (control) { // A branch/call inside the template means subsequent instructions may be reached // out of textual order; stop trusting the linear def model past this point. @@ -1809,7 +1888,6 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm asm_acc->impure_reason_node = instr->name; } } - return; } @@ -2466,6 +2544,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity ptr_set_init(&asm_acc.defined_params); defer (ptr_set_destroy(&asm_acc.defined_params)); + map_init(&asm_acc.instruction_facts); + defer (map_destroy(&asm_acc.instruction_facts)); + // Physical registers known to hold a defined value at the current point in the // straight-line instruction stream. Seeded with input-pinned registers (they From 322f59dae002f1791a6a6b61695daf205f644c6e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 21:49:32 +0100 Subject: [PATCH 31/54] Implement a CFG for the assembler to improve the soundness of the checks --- .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 15 + .../x86/tablegen/cpp-compiler/cpp-gen.odin | 39 ++ src/asm_tables_amd64.cpp | 35 ++ src/asm_tables_riscv.cpp | 11 + src/check_asm.cpp | 261 ++------- src/check_asm_cfg.cpp | 541 ++++++++++++++++++ src/entity.cpp | 3 + 7 files changed, 681 insertions(+), 224 deletions(-) create mode 100644 src/check_asm_cfg.cpp diff --git a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin index dbd9a4ca5..f4f70d9be 100644 --- a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin @@ -821,6 +821,21 @@ main :: proc() { } """) + strings.write_string(&sb, """ + bool is_self_zeroing_idiom(u16 m) const { + switch (m) { + case M_XOR: + case M_SUB: + case M_SUBW: + case M_SLT: + case M_SLTU: + case M_ANDN: + return true; + } + return false; + } + """) + strings.write_string(&sb, "\n};\n") strings.write_string(&sb, "\n\n\n") diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 084f0acff..d64c6b2e4 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -824,6 +824,45 @@ main :: proc() { } """) + strings.write_string(&sb, """ + bool is_self_zeroing_idiom(u16 m) const { + switch (m) { + // integer xor / sub: x ^ x == 0, x - x == 0 + case M_XOR: + case M_SUB: + + // SSE/AVX bitwise xor of a register with itself + case M_PXOR: + case M_XORPS: + case M_XORPD: + case M_VPXOR: + case M_VXORPS: + case M_VXORPD: + + // packed integer subtract: psub x, x == 0 + case M_PSUBB: + case M_PSUBW: + case M_PSUBD: + case M_PSUBQ: + case M_VPSUBB: + case M_VPSUBW: + case M_VPSUBD: + case M_VPSUBQ: + + // andnot of a value with itself: (~x) & x == 0 + case M_ANDN: // BMI1 GPR: andn dst, a, a + case M_ANDNPS: + case M_ANDNPD: + case M_PANDN: + case M_VANDNPS: + case M_VANDNPD: + case M_VPANDN: + return true; + } + return false; + } + """) + strings.write_string(&sb, "\n};\n") strings.write_string(&sb, "\n\n\n") diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 1302c7c33..4fd0d03e6 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -813,6 +813,41 @@ struct Asm_amd64 { break; } return {AsmOperandConstraint_None, -1}; + } bool is_self_zeroing_idiom(u16 m) const { + switch (m) { + // integer xor / sub: x ^ x == 0, x - x == 0 + case M_XOR: + case M_SUB: + + // SSE/AVX bitwise xor of a register with itself + case M_PXOR: + case M_XORPS: + case M_XORPD: + case M_VPXOR: + case M_VXORPS: + case M_VXORPD: + + // packed integer subtract: psub x, x == 0 + case M_PSUBB: + case M_PSUBW: + case M_PSUBD: + case M_PSUBQ: + case M_VPSUBB: + case M_VPSUBW: + case M_VPSUBD: + case M_VPSUBQ: + + // andnot of a value with itself: (~x) & x == 0 + case M_ANDN: // BMI1 GPR: andn dst, a, a + case M_ANDNPS: + case M_ANDNPD: + case M_PANDN: + case M_VANDNPS: + case M_VANDNPD: + case M_VPANDN: + return true; + } + return false; } }; diff --git a/src/asm_tables_riscv.cpp b/src/asm_tables_riscv.cpp index 85714c37e..62fddbda9 100644 --- a/src/asm_tables_riscv.cpp +++ b/src/asm_tables_riscv.cpp @@ -755,6 +755,17 @@ struct Asm_riscv { break; } return {AsmOperandConstraint_None, -1}; + } bool is_self_zeroing_idiom(u16 m) const { + switch (m) { + case M_XOR: + case M_SUB: + case M_SUBW: + case M_SLT: + case M_SLTU: + case M_ANDN: + return true; + } + return false; } }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 1f2517210..e57839569 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1,63 +1,4 @@ -struct AsmBlock { - i32 first, last; - Array succs; - u16 in_defs; - u16 out_defs; - PtrSet in_params; - PtrSet out_params; - bool reachable; -}; - -struct AsmInstructionFacts { - AstAsmInstruction *node; - String name; - - u16 gen_regs; - u16 read_regs; - - Array gen_params; - Array read_params; - - bool is_control; - bool is_conditional; - bool is_terminal; - - Entity *branch_target; - i32 block_id; -}; - - -struct AsmMnemonicAccumulator { - u16 defined_regs; - PtrSet defined_params; - - // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). - u16 implicit_clobbered_regs; - u16 explicitly_produced_regs; - u16 stale_outputs; - - bool straight_line; - - // Whether the most-recently-checked instruction terminates straight-line flow. - // Reset to false at every label (a label starts a fresh straight-line region whose - // tail we haven't seen yet). Consulted after the loop for #diverging templates. - bool last_is_terminal; - - // Did the template contain any instructions at all? An empty diverging body can't diverge. - bool saw_any_instructions; - - // Related to #align_stack - // any call/branch (CONTROL) or memory effect that could require the stack - // to be realigned. If none occurred, #align_stack is redundant. - bool saw_call_or_mem; - - // Purity test - bool can_be_pure; - char const *impure_reason; - Ast * impure_reason_node; - - PtrMap instruction_facts; -}; +#include "check_asm_cfg.cpp" // Bit-width the operand's Odin type occupies in a register/immediate slot. // Integers/floats/bools/pointers -> their size; #simd -> total vector width. 0 if unknown. @@ -1647,51 +1588,6 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } } - if (asm_acc->straight_line) { - u16 wants = cast(u16)clobber.implicit_rd & asm_ctx->CLOBBER_REGS_NAMED; - u16 undefined = wants & ~asm_acc->defined_regs; - - for (u16 bit = 1; bit != 0; bit <<= 1) { - if ((undefined & bit) == 0) { - continue; - } - char const *rname = asm_ctx->clobber_reg_bit_name(bit); - - String owner = {}; - char const *role = nullptr; - for (auto const &ed : tmpl_entity->AsmTemplate.decls) { - if (ed.pin.len == 0 || ed.entity == nullptr) { - continue; - } - if (asm_ctx->clobber_bit_for_reg_name(ed.pin) != bit) { - continue; - } - if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) { - owner = ed.entity->token.string; - role = "output"; - break; - } - if (ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0) { - owner = ed.entity->token.string; - role = "scratch"; - break; - } - } - - if (role != nullptr) { - error(instr->name, - "'%.*s' implicitly reads %%%s, which is bound to the %s parameter '%.*s', " - "but nothing has written %%%s yet; write to it (e.g. into '%.*s') before this instruction", - LIT(name), rname, role, LIT(owner), rname, LIT(owner)); - } else { - error(instr->name, - "'%.*s' implicitly reads %%%s, but nothing in this template produces a value for it; " - "pin an input parameter to %%%s, or write %%%s before this instruction", - LIT(name), rname, rname, rname); - } - } - } - u16 produced = cast(u16)clobber.implicit_wr & asm_ctx->CLOBBER_REGS_NAMED; u16 explicit_writes = 0; @@ -1762,7 +1658,28 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } facts.gen_regs = produced | pinned_param_writes; - asm_acc->defined_regs |= facts.gen_regs; + + // NOTE(bill): mnemonics such as `xor r, r` / `sub r, r` act as zeroing the destination + // independent of its prior value: the read is architecturally dead, so it must not count as a use. + bool self_zeroing = false; + if (asm_ctx->is_self_zeroing_idiom(cast(u16)mnemonic) && operands.count >= 2) { + Entity *e0 = entity_of_node(operands[0].expr); + bool all_same = (e0 != nullptr); + for (isize k = 1; all_same && k < operands.count; k++) { + all_same = entity_of_node(operands[k].expr) == e0; + } + // also treat literal %reg == %reg as self-zeroing (no entity, compare reg bits) + if (!all_same && operands[0].expr->kind == Ast_AsmRegister) { + u16 b0 = asm_ctx->clobber_bit_for_reg_name(operands[0].expr->AsmRegister.name.string); + all_same = b0 != 0; + for (isize k = 1; all_same && k < operands.count; k++) { + all_same = operands[k].expr->kind == Ast_AsmRegister && + asm_ctx->clobber_bit_for_reg_name(operands[k].expr->AsmRegister.name.string) == b0; + } + } + self_zeroing = all_same; + } + for_array(i, operands) { int slot = user_operand_target_index(cast(int)i); @@ -1773,7 +1690,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm if (pe == nullptr || pe->kind != Entity_Variable) { continue; } - if (cast(u16)clobber.read & (1u << slot)) { + + if (!self_zeroing && (cast(u16)clobber.read & (1u << slot))) { array_add(&facts.read_params, pe); } if (cast(u16)clobber.written & (1u << slot)) { @@ -1781,40 +1699,6 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } } - if (asm_acc->straight_line) { - // NOTE(bill): check for read-before-write (use of undefined value) - // Only really meaningful in straight-line code, so a label above means a branch - // could have defined the value out of the textual order - for_array(i, operands) { - auto const &op = operands[i]; - int slot = user_operand_target_index(cast(int)i); - if (slot < 0 || (cast(u16)clobber.read & (1u << slot)) == 0) { - continue; // not a read slot of this form - } - Entity *pe = entity_of_node(op.expr); - if (pe == nullptr || pe->kind != Entity_Variable) { - continue; // literal %reg / immediate / memory, not a tracked param - } - if (!ptr_set_exists(&asm_acc->defined_params, pe)) { - error(op.expr, "'%.*s' reads '%.*s' before it is assigned; its initial value is undefined", - LIT(name), LIT(pe->token.string)); - ptr_set_add(&asm_acc->defined_params, pe); // warn once per param - } - } - } - - // NOTE(bill): record the instruction's parameter writes - for_array(i, operands) { - int slot = user_operand_target_index(cast(int)i); - if (slot < 0 || (cast(u16)clobber.written & (1u << slot)) == 0) { - continue; - } - Entity *pe = entity_of_node(operands[i].expr); - if (pe != nullptr && pe->kind == Entity_Variable) { - ptr_set_add(&asm_acc->defined_params, pe); - } - } - { // Registers this form clobbers implicitly (RDTSC->RAX:RDX, etc.), for the // redundant-#clobber hint. Union across the template; pinned regs excluded @@ -1842,17 +1726,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm bool halt = clobber.has_halt(); // A conditional branch reads a flag and can fall through -> not terminal. bool conditional = clobber.is_conditional(); - asm_acc->last_is_terminal = halt || (control && !conditional); facts.is_control = control; facts.is_conditional = conditional; facts.is_terminal = halt || (control && !conditional); - - if (control) { - // A branch/call inside the template means subsequent instructions may be reached - // out of textual order; stop trusting the linear def model past this point. - asm_acc->straight_line = false; - } } asm_ctx->clobber_implicit_regs(&tmpl_entity->AsmTemplate.clobber_registers_set, produced); @@ -2426,7 +2303,6 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity entity->type = type; - bool is_volatile = false; bool is_align_stack = false; bool is_pure_annotated = false; @@ -2541,44 +2417,10 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } AsmMnemonicAccumulator asm_acc = {}; - ptr_set_init(&asm_acc.defined_params); - defer (ptr_set_destroy(&asm_acc.defined_params)); - map_init(&asm_acc.instruction_facts); defer (map_destroy(&asm_acc.instruction_facts)); - - // Physical registers known to hold a defined value at the current point in the - // straight-line instruction stream. Seeded with input-pinned registers (they - // carry their argument at entry); grows as instructions write registers. - for (auto const &ed : ate->decls) { - if (ed.no_init) { - ptr_set_add(&asm_acc.defined_params, ed.entity); - } - switch (ed.param_group) { - case AsmTemplateEntityDeclParamGroup_Input: - if (ed.pin.len != 0) { - // Only inputs (and the input half of a tie, which is Input-group) hold a - // value at entry. Output/scratch pins start undefined and become defined - // when an instruction writes them. - asm_acc.defined_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); - } - ptr_set_add(&asm_acc.defined_params, ed.entity); - break; - case AsmTemplateEntityDeclParamGroup_Output: - if (ed.tie >= 0) { - ptr_set_add(&asm_acc.defined_params, ed.entity); - } - break; - } - } - - // Linear "written earlier in the text" is only a sound proxy for "produced at - // runtime" while control flow is straight-line. The first label is a potential - // jump target / back-edge, after which a read can precede its textual def; from - // there on we stop emitting the implicit-read diagnostic. - asm_acc.straight_line = true; - asm_acc.can_be_pure = true; + asm_acc.can_be_pure = true; // collect label decls for (Ast *instruction_ : at->instructions) { @@ -2678,10 +2520,6 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity case_end; case_ast_node(label, AsmLabelDecl, instruction_); - asm_acc.straight_line = false; - // A new straight-line region begins here; its tail is unseen, - // so the previous instruction's terminality no longer describes the body's end. - asm_acc.last_is_terminal = false; if (previous_prefix != 0) { error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but a label declaration was found"); previous_prefix = 0; @@ -2780,32 +2618,17 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but the template ended"); } - for (auto const &ed : ate->decls) { - if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) { - continue; - } - if (ed.tie >= 0) { - continue; - } - if (ed.no_init) { - continue; - } - if (!asm_acc.straight_line) { - continue; - } + // NOTE(bill, 2026-08-24): Construct a control-flow graph (CFG) from the instructions + // to do further analysis which is not possible with an conservative straight-line approximation + // Using a CFG is a much sounder approach for calculating: + // * reads before writes + // * divergence + // * unreachable code - bool written = false; - if (ed.pin.len != 0) { - u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); - written = (bit != 0) && (asm_acc.defined_regs & bit) != 0; - } else { - written = ptr_set_exists(&asm_acc.defined_params, ed.entity); - } - - if (!written) { - error(ed.entity->token, "'asm' output parameter '%.*s' is never assigned to in this template, thus its value is undefined", LIT(ed.entity->token.string)); - } - } + AsmCfg cfg = {}; + defer (asm_cfg_destroy(&cfg)); + check_asm_cfg_build(d->init_expr, &asm_acc, &cfg); + check_asm_cfg_analyse(asm_ctx, ctx, entity, &cfg, &asm_acc); bool vet_unused = false; @@ -2866,7 +2689,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } } if (ed.tie > 0) { - // TODO(bill): Handle this edge case + // TODO(bill): Handle this edge case? continue; } @@ -2893,16 +2716,6 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity "that would require the stack to be realigned"); } - if (type->Proc.diverging) { - if (!asm_acc.saw_any_instructions) { - error(entity->token, "This asm template is declared as diverging (-> !) but its body is empty and cannot diverge"); - } else if (!asm_acc.last_is_terminal) { - error(entity->token, - "This asm template is declared diverging (-> !) but its final instruction can fall through; " - "end it with an unconditional jump, return, or halt"); - } - } - { bool declared_effects = entity->AsmTemplate.is_volatile || entity->AsmTemplate.clobber_memory || diff --git a/src/check_asm_cfg.cpp b/src/check_asm_cfg.cpp new file mode 100644 index 000000000..a02994ca6 --- /dev/null +++ b/src/check_asm_cfg.cpp @@ -0,0 +1,541 @@ +struct AsmBlock { + i32 first, last; + Array succs; + u16 in_defs; + u16 out_defs; + PtrSet in_params; + PtrSet out_params; + bool reachable; +}; + +struct AsmInstructionFacts { + AstAsmInstruction *node; + String name; + + u16 gen_regs; + u16 read_regs; + + Array gen_params; + Array read_params; + + bool is_control; + bool is_conditional; + bool is_terminal; + + Entity *branch_target; + i32 block_id; +}; + + +struct AsmMnemonicAccumulator { + // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). + u16 implicit_clobbered_regs; + u16 explicitly_produced_regs; + u16 stale_outputs; + + bool saw_any_instructions; // NOTE(bill): An empty diverging body cannot diverge. + + // NOTE(bill): Related to #align_stack + // any call/branch (CONTROL) or memory effect that could require the stack + // to be realigned. If none occurred, #align_stack is redundant. + bool saw_call_or_mem; + + // Purity test + bool can_be_pure; + char const *impure_reason; + Ast * impure_reason_node; + + PtrMap instruction_facts; +}; + +struct AsmCfg { + Array insts; // program-order (only for fact-carrying instrs) + Array blocks; + PtrMap label_block; // key: Entity_Label* +}; + +gb_internal void asm_cfg_destroy(AsmCfg *cfg) { + for (auto &block : cfg->blocks) { + array_free(&block.succs); + ptr_set_destroy(&block.in_params); + ptr_set_destroy(&block.out_params); + } + array_free(&cfg->blocks); + array_free(&cfg->insts); + map_destroy(&cfg->label_block); +} + +gb_internal void check_asm_cfg_build(Ast *at_node, AsmMnemonicAccumulator *acc, AsmCfg *cfg) { + ast_node(at, AsmTemplate, at_node); + + cfg->insts.allocator = heap_allocator(); + cfg->blocks.allocator = heap_allocator(); + map_init(&cfg->label_block); + + bool need_leader = true; + + + // Build basic blocks over the template body. A leader is: the first instruction, any + // instruction preceded by a label, and any instruction following a control transfer. + for (Ast *node : at->instructions) { + if (node->kind == Ast_AsmLabelDecl) { + // Every label between two instructions names the block the *next* instruction + // opens; consecutive labels share it. A trailing label maps to blocks.count. + Entity *le = node->AsmLabelDecl.name->Ident.entity; + if (le != nullptr) { + map_set(&cfg->label_block, le, cast(i32)cfg->blocks.count); + } + need_leader = true; + continue; + } + if (node->kind != Ast_AsmInstruction) { + continue; // directives are straight-line filler; no CFG effect + } + + AstAsmInstruction *instr = &node->AsmInstruction; + AsmInstructionFacts *facts = map_get(&acc->instruction_facts, instr); + // Prefixes and pseudo-macro ops (li/la) carry no facts and never branch. + + if (need_leader || cfg->blocks.count == 0) { + AsmBlock b = {}; + b.first = cast(i32)cfg->insts.count; + b.last = cast(i32)cfg->insts.count; + b.succs.allocator = heap_allocator(); + array_add(&cfg->blocks, b); + need_leader = false; + } + + i32 bi = cast(i32)cfg->blocks.count - 1; + i32 ii = cast(i32)cfg->insts.count; + array_add(&cfg->insts, instr); + cfg->blocks[bi].last = ii; + + if (facts != nullptr) { + facts->block_id = bi; + if (facts->is_control) { + need_leader = true; // the fall-through after a branch starts a new block + } + } + } + + for_array(bi, cfg->blocks) { // Calculate the edges for the blocks + AsmBlock *b = &cfg->blocks[bi]; + + AstAsmInstruction *last = cfg->insts[b->last]; + AsmInstructionFacts *lf = map_get(&acc->instruction_facts, last); + + i32 branch_succ = -1; + bool fallthrough = true; + + if (lf != nullptr && lf->is_control) { + if (lf->branch_target != nullptr) { + i32 *t = map_get(&cfg->label_block, lf->branch_target); + if (t != nullptr && *t < cast(i32)cfg->blocks.count) { + branch_succ = *t; // in-range internal target ('jmp .l' / 'jz .l') + } + // For `t == blocks.count`, this implies a jump to the implicit end, and is handled as "leaves" below + } + // e.g. jmp/ret/hlt (and, conservatively, call) do not fall through in this model. + if (lf->is_terminal) { + fallthrough = false; + } + } + + if (branch_succ >= 0) { + array_add(&b->succs, branch_succ); + } + if (fallthrough) { + i32 next = cast(i32)bi + 1; + if (next < cast(i32)cfg->blocks.count) { + array_add(&b->succs, next); + } + } + } + + if (cfg->blocks.count != 0) { // Reachability determination + Array stack = {}; + stack.allocator = heap_allocator(); + defer (array_free(&stack)); + + cfg->blocks[0].reachable = true; + array_add(&stack, cast(i32)0); + while (stack.count > 0) { + i32 bi = stack[stack.count-1]; + stack.count -= 1; + for (i32 s : cfg->blocks[bi].succs) { + if (s >= 0 && s < cast(i32)cfg->blocks.count && !cfg->blocks[s].reachable) { + cfg->blocks[s].reachable = true; + array_add(&stack, s); + } + } + } + } +} + +gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, AsmMnemonicAccumulator *acc, i32 bi) { + AsmBlock const *b = &cfg->blocks[bi]; + AstAsmInstruction *last = cfg->insts[b->last]; + AsmInstructionFacts *lf = map_get(&acc->instruction_facts, last); + + if (lf != nullptr && lf->branch_target != nullptr) { + i32 *t = map_get(&cfg->label_block, lf->branch_target); + if (t != nullptr && *t >= cast(i32)cfg->blocks.count) { + return true; // 'jmp .end' — falls into the implicit return + } + } + bool terminal = (lf != nullptr) && lf->is_terminal; + if (!terminal && bi > cast(i32)cfg->blocks.count) { + return true; // straight-line / conditional tail with nothing after it + } + return false; +} + +template +gb_internal void check_asm_cfg_report_undef_reg(AsmCtx *asm_ctx, Entity *tmpl_entity, + AstAsmInstruction *instr, String name, u16 bit) { + char const *rname = asm_ctx->clobber_reg_bit_name(bit); + String owner = {}; + char const *role = nullptr; + for (auto const &ed : tmpl_entity->AsmTemplate.decls) { + if (ed.pin.len == 0 || ed.entity == nullptr) { + continue; + } + if (asm_ctx->clobber_bit_for_reg_name(ed.pin) != bit) { + continue; + } + if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) { + owner = ed.entity->token.string; + role = "output"; + break; + } + if (ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0) { + owner = ed.entity->token.string; + role = "scratch"; + break; + } + } + if (role != nullptr) { + error(instr->name, + "'%.*s' implicitly reads %%%s, which is bound to the %s parameter '%.*s', " + "but nothing writes %%%s on all paths reaching here; write to it (e.g. into '%.*s') first", + LIT(name), rname, role, LIT(owner), rname, LIT(owner)); + } else { + error(instr->name, + "'%.*s' implicitly reads %%%s, but nothing in this template produces a value for it " + "on all paths reaching here; pin an input to %%%s, or write %%%s first", + LIT(name), rname, rname, rname); + } +} + +template +gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *entity, AsmCfg *cfg, + AsmMnemonicAccumulator *acc) { + GB_ASSERT(entity->kind == Entity_AsmTemplate); + auto const &decls = entity->AsmTemplate.decls; + bool diverging = entity->type->Proc.diverging; + + if (cfg->blocks.count == 0) { + // With an empty body, the CFG cannot really do nothing + if (diverging && !acc->saw_any_instructions) { + error(entity->token, "This asm template is declared as diverging (-> !) but its body is empty and cannot diverge"); + } + return; + } + + if (decls.count > 64) { + error(entity->token, "'asm' templates cannot have more than 64 total parameter declarations, got %td", decls.count); + return; + } + u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED; + + PtrMap entity_to_index = {}; + map_init(&entity_to_index); + defer (map_destroy(&entity_to_index)); + u64 universe_pm = 0; + for_array(i, decls) { + if (decls[i].entity != nullptr) { + map_set(&entity_to_index, decls[i].entity, cast(i32)i); + universe_pm |= (cast(u64)1 << i); + } + } + auto bit_of = [&](Entity *e) -> u64 { + i32 *ix = map_get(&entity_to_index, e); + return ix ? (cast(u64)1 << *ix) : cast(u64)0; + }; + + // NOTE(bill): entry seed intiailization which mirrors the linear seeding of defined_regs + u16 seed_regs = 0; + u64 seed_pm = 0; + for (auto const &ed : decls) { + if (ed.no_init) { + seed_pm |= bit_of(ed.entity); + if (ed.pin.len != 0) { + seed_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); + } + } + switch (ed.param_group) { + case AsmTemplateEntityDeclParamGroup_Input: + seed_pm |= bit_of(ed.entity); + if (ed.pin.len != 0) { + seed_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); + } + break; + case AsmTemplateEntityDeclParamGroup_Output: + // NOTE(bill): input provides the value + if (ed.tie >= 0) { + seed_pm |= bit_of(ed.entity); + } + break; + } + } + + isize const n = cfg->blocks.count; + + auto in_regs = slice_make(heap_allocator(), n); defer (slice_free(&in_regs, heap_allocator())); + auto out_regs = slice_make(heap_allocator(), n); defer (slice_free(&out_regs, heap_allocator())); + auto gen_regs = slice_make(heap_allocator(), n); defer (slice_free(&gen_regs, heap_allocator())); + auto in_pm = slice_make(heap_allocator(), n); defer (slice_free(&in_pm, heap_allocator())); + auto out_pm = slice_make(heap_allocator(), n); defer (slice_free(&out_pm, heap_allocator())); + auto gen_pm = slice_make(heap_allocator(), n); defer (slice_free(&gen_pm, heap_allocator())); + + // predecessors, restricted to reachable blocks + auto preds = slice_make>(heap_allocator(), n); + for_array(i, preds) { + preds[i].allocator = heap_allocator(); + } + defer ({ + for_array(i, preds) { + array_free(&preds[i]); + } + slice_free(&preds, heap_allocator()); + }); + for_array(bi, cfg->blocks) { + AsmBlock *block = &cfg->blocks[bi]; + if (!block->reachable) { + continue; + } + for (i32 s : block->succs) { + if (0 <= s && s < cast(i32)n && + cfg->blocks[s].reachable) { + array_add(&preds[s], cast(i32)bi); + } + } + } + + for_array(bi, cfg->blocks) { + u16 gr = 0; + u64 gp = 0; + AsmBlock const &b = cfg->blocks[bi]; + for (i32 ii = b.first; ii <= b.last; ii++) { + AsmInstructionFacts *f = map_get(&acc->instruction_facts, cfg->insts[ii]); + if (f == nullptr) { + continue; + } + gr |= f->gen_regs; + for (Entity *pe : f->gen_params) { + gp |= bit_of(pe); + } + } + gen_regs[bi] = gr; + gen_pm[bi] = gp; + } + + // NOTE(bill): initialize the blocks + // entry is from the seeds and every other reachable block from TOP (intersection) + for_array(bi, cfg->blocks) { + if (!cfg->blocks[bi].reachable) { + continue; + } + if (bi == 0) { + in_regs[bi] = seed_regs; + in_pm[bi] = seed_pm; + } else { + in_regs[bi] = REG_TOP; + in_pm[bi] = universe_pm; + } + out_regs[bi] = in_regs[bi] | gen_regs[bi]; + out_pm[bi] = in_pm[bi] | gen_pm[bi]; + } + + // forward must-analysis: in = AND(preds.out); out = in | gen. Iterate to fixpoint. + bool changed = true; + while (changed) { + changed = false; + for_array(bi, cfg->blocks) { + if (!cfg->blocks[bi].reachable) { + continue; + } + + u16 nin_r = seed_regs; + u64 nin_p = seed_pm; + if (bi != 0) { + nin_r = REG_TOP; + nin_p = universe_pm; + for (i32 p : preds[bi]) { + nin_r &= out_regs[p]; + nin_p &= out_pm[p]; + } + } + u16 nout_r = nin_r | gen_regs[bi]; + u64 nout_p = nin_p | gen_pm[bi]; + + if (nin_r != in_regs[bi] || + nin_p != in_pm[bi] || + nout_r != out_regs[bi] || + nout_p != out_pm[bi]) { + in_regs[bi] = nin_r; + in_pm[bi] = nin_p; + out_regs[bi] = nout_r; + out_pm[bi] = nout_p; + changed = true; + } + } + } + + // NOTE(bill): publish the register masks and materialise the parameter sets onto the blocks + for_array(bi, cfg->blocks) { + AsmBlock *b = &cfg->blocks[bi]; + b->in_defs = in_regs[bi]; + b->out_defs = out_regs[bi]; + if (!b->reachable) { + continue; + } + for_array(i, decls) { + Entity *e = decls[i].entity; + if (e == nullptr) { + continue; + } + if (((in_pm[bi] >> i) & 1) != 0) { + ptr_set_add(&b->in_params, e); + } + if (((out_pm[bi] >> i) & 1) != 0) { + ptr_set_add(&b->out_params, e); + } + } + } + + // NOTE(bill): unreachable code + for (AsmBlock &block : cfg->blocks) { + if (block.reachable) { + continue; + } + AstAsmInstruction *first = cfg->insts[block.first]; + if (block.first == block.last) { + warning(first->name, "The asm instruction is unreachable within this block"); + } else { + warning(first->name, "The asm instructions are unreachable within this block"); + } + } + + { // NOTE(bill): read-before-write, definite-assignment across the whole CFG + PtrSet reported_params = {}; + defer (ptr_set_destroy(&reported_params)); + + u16 reported_regs = 0; + + for_array(bi, cfg->blocks) { + AsmBlock const &b = cfg->blocks[bi]; + if (!b.reachable) { + continue; + } + + u16 run_regs = in_regs[bi]; + u64 run_pm = in_pm[bi]; + + for (i32 ii = b.first; ii <= b.last; ii++) { + AstAsmInstruction *instr = cfg->insts[ii]; + AsmInstructionFacts *f = map_get(&acc->instruction_facts, instr); + if (f == nullptr) { + continue; + } + + u16 undef = f->read_regs & REG_TOP & ~run_regs & ~reported_regs; + for (u16 bit = 1; bit != 0; bit <<= 1) { + if ((undef & bit) == 0) { + continue; + } + check_asm_cfg_report_undef_reg(asm_ctx, entity, instr, f->name, bit); + reported_regs |= bit; + } + + for (Entity *pe : f->read_params) { + i32 *ix = map_get(&entity_to_index, pe); + if (ix == nullptr) { + continue; + } + if (((run_pm >> *ix) & 1) == 0 && !ptr_set_exists(&reported_params, pe)) { + Ast *loc = instr->name; + for (Ast *op : instr->operands) { + if (entity_of_node(op) == pe) { loc = op; break; } + } + error(loc, "'%.*s' reads '%.*s' before it is assigned; its initial value is undefined", LIT(f->name), LIT(pe->token.string)); + ptr_set_add(&reported_params, pe); + } + } + + run_regs |= f->gen_regs; + for (Entity *pe : f->gen_params) { + run_pm |= bit_of(pe); + } + } + } + } + + { // NOTE(bill): Collect the template's return points reachable blocks that leave via the end + u16 exit_regs = REG_TOP; + u64 exit_pm = universe_pm; + bool any_exit = false; + for_array(bi, cfg->blocks) { + if (!cfg->blocks[bi].reachable) { + continue; + } + if (!check_asm_cfg_block_leaves(cfg, acc, cast(i32)bi)) { + continue; + } + any_exit = true; + exit_regs &= out_regs[bi]; + exit_pm &= out_pm[bi]; + } + + // NOTE(bill): Outputs must be assigned on every path that returns + if (any_exit && !diverging) { + for (auto const &ed : decls) { + if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) { + continue; + } + if (ed.tie >= 0 || ed.no_init) { + continue; + } + + bool written; + if (ed.pin.len != 0) { + u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); + written = (bit != 0) && (exit_regs & bit) != 0; + } else { + written = (exit_pm & bit_of(ed.entity)) != 0; + } + if (!written) { + error(ed.entity->token, + "'asm' output parameter '%.*s' is not assigned on all paths through this template; " + "its value is undefined", + LIT(ed.entity->token.string)); + } + } + } + } + + if (diverging) { // No reachable path may return / fall off the end + bool any_leak = false; + for_array(bi, cfg->blocks) { + if (cfg->blocks[bi].reachable && check_asm_cfg_block_leaves(cfg, acc, cast(i32)bi)) { + any_leak = true; + break; + } + } + if (any_leak) { + error(entity->token, + "This asm template is declared diverging (-> !) but a reachable path can fall through the end; " + "end every path with an unconditional jump, return, or halt"); + } + } +} \ No newline at end of file diff --git a/src/entity.cpp b/src/entity.cpp index b70f09045..95b5bf6b7 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -342,6 +342,8 @@ struct Entity { String name; Ast *node; Ast *parent; + + i32 asm_block_index; } Label; struct { Ast *node; @@ -577,6 +579,7 @@ gb_internal Entity *alloc_entity_label(Scope *scope, Token token, Type *type, As Entity *entity = alloc_entity(Entity_Label, scope, token, type); entity->Label.node = node; entity->Label.parent = parent; + entity->Label.asm_block_index = -1; entity->state = EntityState_Resolved; return entity; } From 7fcf65d2c2cc65dcfb0de9b2b075a513cb698c51 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 22:13:57 +0100 Subject: [PATCH 32/54] asm: General clean up of the CFG code and remove redundant calculations --- src/check_asm.cpp | 114 ++++++++++++---------------------- src/check_asm_cfg.cpp | 141 +++++++++++++++++++++++++++--------------- 2 files changed, 132 insertions(+), 123 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index e57839569..2b0fde8d7 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1110,7 +1110,7 @@ template gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, u16 mnemonic, u16 pseudo_mnemonic, Slice const &operands, u8 previous_prefix, Ast *previous_prefix_instr, - AsmMnemonicAccumulator *asm_acc) { + AsmCfg *cfg) { GB_ASSERT(mnemonic > 0); auto forms = asm_ctx->encoding_forms(mnemonic); auto clobber_forms = asm_ctx->clobber_forms(mnemonic); @@ -1140,7 +1140,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm break; } - map_set(&asm_acc->instruction_facts, instr, facts); + map_set(&cfg->instruction_facts, instr, facts); }); @@ -1578,14 +1578,12 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // through a parameter pointer does NOT require stack realignment, so // implies_clobber_memory() is intentionally NOT used here. if (clobber.is_call_or_mem()) { - asm_acc->saw_call_or_mem = true; + cfg->saw_call_or_mem = true; } u16 pinned_mask = 0; - for (auto const &ed : tmpl_entity->AsmTemplate.decls) { - if (ed.pin.len != 0) { - pinned_mask |= asm_ctx->clobber_bit_for_reg_name(ed.pin); - } + for_array(i, tmpl_entity->AsmTemplate.decls) { + pinned_mask |= asm_decl_resolve_pin_bit(asm_ctx, tmpl_entity->AsmTemplate.decls, cast(i32)i); } u16 produced = cast(u16)clobber.implicit_wr & asm_ctx->CLOBBER_REGS_NAMED; @@ -1593,50 +1591,25 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm u16 written_ops = cast(u16)clobber.written; u16 pinned_param_writes = 0; + auto const &decls = tmpl_entity->AsmTemplate.decls; for_array(i, operands) { int tslot = user_operand_target_index(cast(int)i); if (tslot < 0 || tslot >= 4 || (written_ops & (1u << tslot)) == 0) { continue; } - auto const &op = operands[i]; - - Ast *e = op.expr; + Ast *e = operands[i].expr; if (e != nullptr && e->kind == Ast_AsmRegister) { u16 b = asm_ctx->clobber_bit_for_reg_name(e->AsmRegister.name.string); produced |= b; explicit_writes |= b; continue; } - - // NOTE(bill): A write through a pinned parameter (or a width-view of one) - // defines that parameter's physical register for the read-before-write check only - auto written_pinned_reg_bit = [&](Operand const &op) -> u16 { - Entity *pe = entity_of_node(op.expr); - if (pe == nullptr || pe->kind != Entity_Variable) { - return 0; - } - auto const &decls = tmpl_entity->AsmTemplate.decls; - for_array(di, decls) { - auto const &ed = decls[di]; - if (ed.entity != pe) { - continue; - } - if (ed.pin.len != 0) { - return asm_ctx->clobber_bit_for_reg_name(ed.pin); - } - // NOTE(bill): A width-view carries no pin of its own and thus it aliases its source's register. - if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) { - String src_pin = decls[ed.view_of].pin; - if (src_pin.len != 0) { - return asm_ctx->clobber_bit_for_reg_name(src_pin); - } - } - return 0; - } - return 0; - }; - - pinned_param_writes |= written_pinned_reg_bit(operands[i]); + Entity *pe = entity_of_node(operands[i].expr); + if (pe != nullptr && pe->kind == Entity_Variable) { + i32 di = -1; + check_asm_find_group(pe, decls, &di); // reuse existing index finder + pinned_param_writes |= asm_decl_resolve_pin_bit(asm_ctx, decls, di); + } } if (is_pseudo && @@ -1704,15 +1677,15 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // redundant-#clobber hint. Union across the template; pinned regs excluded // so a legitimate output pin is never called "redundant". u16 implicit_wr = cast(u16)clobber.implicit_wr & asm_ctx->CLOBBER_REGS_NAMED; - asm_acc->implicit_clobbered_regs |= implicit_wr & ~pinned_mask; + cfg->implicit_clobbered_regs |= implicit_wr & ~pinned_mask; // Approximate staleness. An output that was explicitly produced (literal %reg write) // and is later implicitly clobbered — without this same instruction re-producing it — // is marked stale. Explicit re-production clears it. Implicitly-produced outputs // (RDTSC->RDX) are never tracked, so they never false-fire. - asm_acc->explicitly_produced_regs |= explicit_writes; - asm_acc->stale_outputs &= ~explicit_writes; - asm_acc->stale_outputs |= implicit_wr & asm_acc->explicitly_produced_regs & ~explicit_writes; + cfg->explicitly_produced_regs |= explicit_writes; + cfg->stale_outputs &= ~explicit_writes; + cfg->stale_outputs |= implicit_wr & cfg->explicitly_produced_regs & ~explicit_writes; } { @@ -1734,7 +1707,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm asm_ctx->clobber_implicit_regs(&tmpl_entity->AsmTemplate.clobber_registers_set, produced); // Purity inference - if (asm_acc->can_be_pure) { + if (cfg->can_be_pure) { // NOTE(bill): Only the first violating instruction is recorded // The later ones don't overwrite the reason. char const *why = nullptr; @@ -1760,9 +1733,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } if (why != nullptr) { - asm_acc->can_be_pure = false; - asm_acc->impure_reason = why; - asm_acc->impure_reason_node = instr->name; + cfg->can_be_pure = false; + cfg->impure_reason = why; + cfg->impure_reason_node = instr->name; } } return; @@ -2416,11 +2389,16 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } } - AsmMnemonicAccumulator asm_acc = {}; - map_init(&asm_acc.instruction_facts); - defer (map_destroy(&asm_acc.instruction_facts)); + // NOTE(bill, 2026-08-24): Construct a control-flow graph (CFG) from the instructions + // to do further analysis which is not possible with an conservative straight-line approximation + // Using a CFG is a much sounder approach for calculating: + // * reads before writes + // * divergence + // * unreachable code - asm_acc.can_be_pure = true; + AsmCfg cfg = {}; + asm_cfg_init(&cfg); + defer (asm_cfg_destroy(&cfg)); // collect label decls for (Ast *instruction_ : at->instructions) { @@ -2484,9 +2462,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity instr->suffix_flags = suffix_flags; check_mnemonic(asm_ctx, ctx, entity, instr, mnemonic, 0, slice_from_array(operands), previous_prefix, previous_prefix_instr, - &asm_acc); + &cfg); - asm_acc.saw_any_instructions = true; + cfg.saw_any_instructions = true; previous_prefix = 0; previous_prefix_instr = nullptr; @@ -2498,9 +2476,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity u16 target_mnemonic = cast(u16)alias.target; check_mnemonic(asm_ctx, ctx, entity, instr, target_mnemonic, pseudo_mnemonic, slice_from_array(operands), previous_prefix, previous_prefix_instr, - &asm_acc); + &cfg); - asm_acc.saw_any_instructions = true; + cfg.saw_any_instructions = true; previous_prefix = 0; previous_prefix_instr = nullptr; @@ -2508,7 +2486,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity instr->suffix_flags = suffix_flags; check_pseudo_macro_mnemonic(asm_ctx, entity, instr, slice_from_array(operands)); - asm_acc.saw_any_instructions = true; + cfg.saw_any_instructions = true; previous_prefix = 0; previous_prefix_instr = nullptr; @@ -2618,18 +2596,8 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but the template ended"); } - // NOTE(bill, 2026-08-24): Construct a control-flow graph (CFG) from the instructions - // to do further analysis which is not possible with an conservative straight-line approximation - // Using a CFG is a much sounder approach for calculating: - // * reads before writes - // * divergence - // * unreachable code - - AsmCfg cfg = {}; - defer (asm_cfg_destroy(&cfg)); - check_asm_cfg_build(d->init_expr, &asm_acc, &cfg); - check_asm_cfg_analyse(asm_ctx, ctx, entity, &cfg, &asm_acc); - + check_asm_cfg_build(asm_ctx, &cfg, d->init_expr, entity); + check_asm_cfg_analyse(asm_ctx, &cfg, ctx, entity); bool vet_unused = false; { @@ -2710,7 +2678,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity "Please add #volatile if the effect is intended."); } - if (entity->AsmTemplate.is_align_stack && !asm_acc.saw_call_or_mem) { + if (entity->AsmTemplate.is_align_stack && !cfg.saw_call_or_mem) { warning(entity->token, "#align_stack is redundant; this template makes no call and touches no memory " "that would require the stack to be realigned"); @@ -2720,12 +2688,12 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity bool declared_effects = entity->AsmTemplate.is_volatile || entity->AsmTemplate.clobber_memory || entity->AsmTemplate.has_observable_side_effect; - bool is_pure = asm_acc.can_be_pure && !declared_effects && !type->Proc.diverging; + bool is_pure = cfg.can_be_pure && !declared_effects && !type->Proc.diverging; entity->AsmTemplate.is_pure = is_pure; if (is_pure_annotated && !is_pure) { - Ast *node = asm_acc.impure_reason_node; - char const *why = asm_acc.impure_reason; + Ast *node = cfg.impure_reason_node; + char const *why = cfg.impure_reason; if (why == nullptr) { if (type->Proc.diverging) { why = "it is declared diverging (-> !) and computes no outputs"; diff --git a/src/check_asm_cfg.cpp b/src/check_asm_cfg.cpp index a02994ca6..8d4e4eb39 100644 --- a/src/check_asm_cfg.cpp +++ b/src/check_asm_cfg.cpp @@ -26,8 +26,7 @@ struct AsmInstructionFacts { i32 block_id; }; - -struct AsmMnemonicAccumulator { +struct AsmCfg { // Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints). u16 implicit_clobbered_regs; u16 explicitly_produced_regs; @@ -46,14 +45,24 @@ struct AsmMnemonicAccumulator { Ast * impure_reason_node; PtrMap instruction_facts; -}; -struct AsmCfg { Array insts; // program-order (only for fact-carrying instrs) Array blocks; PtrMap label_block; // key: Entity_Label* + + PtrMap entity_to_index; + Array decl_pin_bit; + u64 universe_pm; }; +gb_internal void asm_cfg_init(AsmCfg *cfg) { + map_init(&cfg->instruction_facts); + map_init(&cfg->entity_to_index); + cfg->decl_pin_bit.allocator = heap_allocator(); + cfg->can_be_pure = true; +}; + + gb_internal void asm_cfg_destroy(AsmCfg *cfg) { for (auto &block : cfg->blocks) { array_free(&block.succs); @@ -63,18 +72,62 @@ gb_internal void asm_cfg_destroy(AsmCfg *cfg) { array_free(&cfg->blocks); array_free(&cfg->insts); map_destroy(&cfg->label_block); + map_destroy(&cfg->instruction_facts); + map_destroy(&cfg->entity_to_index); + array_free(&cfg->decl_pin_bit); } -gb_internal void check_asm_cfg_build(Ast *at_node, AsmMnemonicAccumulator *acc, AsmCfg *cfg) { +// The physical-register bit a decl is pinned to. A width-view carries no pin of +// its own; it inherits its source decl's pin. Returns 0 for unpinned decls. +template +gb_internal u16 asm_decl_resolve_pin_bit(AsmCtx *asm_ctx, Array const &decls, i32 di) { + if (di < 0 || di >= cast(i32)decls.count) { + return 0; + } + auto const &ed = decls[di]; + if (ed.pin.len != 0) { + return asm_ctx->clobber_bit_for_reg_name(ed.pin); + } + if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) { + String src_pin = decls[ed.view_of].pin; + if (src_pin.len != 0) { + return asm_ctx->clobber_bit_for_reg_name(src_pin); + } + } + return 0; +} + +template +gb_internal void asm_cfg_populate_decls(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *entity) { + auto const &decls = entity->AsmTemplate.decls; + cfg->universe_pm = 0; + if (decls.count > 64) { + // NOTE(bill): check_asm_cfg_analyse will err on this since this is exceed the maximum number of declarations + return; + } + array_resize(&cfg->decl_pin_bit, decls.count); + for_array(i, decls) { + Entity *e = decls[i].entity; + cfg->decl_pin_bit[i] = asm_decl_resolve_pin_bit(asm_ctx, decls, cast(i32)i); + if (e != nullptr) { + map_set(&cfg->entity_to_index, e, cast(i32)i); + cfg->universe_pm |= (cast(u64)1 << i); + } + } +} + +template +gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, Entity *entity) { ast_node(at, AsmTemplate, at_node); + asm_cfg_populate_decls(asm_ctx, cfg, entity); + cfg->insts.allocator = heap_allocator(); cfg->blocks.allocator = heap_allocator(); map_init(&cfg->label_block); bool need_leader = true; - // Build basic blocks over the template body. A leader is: the first instruction, any // instruction preceded by a label, and any instruction following a control transfer. for (Ast *node : at->instructions) { @@ -93,7 +146,7 @@ gb_internal void check_asm_cfg_build(Ast *at_node, AsmMnemonicAccumulator *acc, } AstAsmInstruction *instr = &node->AsmInstruction; - AsmInstructionFacts *facts = map_get(&acc->instruction_facts, instr); + AsmInstructionFacts *facts = map_get(&cfg->instruction_facts, instr); // Prefixes and pseudo-macro ops (li/la) carry no facts and never branch. if (need_leader || cfg->blocks.count == 0) { @@ -122,7 +175,7 @@ gb_internal void check_asm_cfg_build(Ast *at_node, AsmMnemonicAccumulator *acc, AsmBlock *b = &cfg->blocks[bi]; AstAsmInstruction *last = cfg->insts[b->last]; - AsmInstructionFacts *lf = map_get(&acc->instruction_facts, last); + AsmInstructionFacts *lf = map_get(&cfg->instruction_facts, last); i32 branch_succ = -1; bool fallthrough = true; @@ -172,10 +225,10 @@ gb_internal void check_asm_cfg_build(Ast *at_node, AsmMnemonicAccumulator *acc, } } -gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, AsmMnemonicAccumulator *acc, i32 bi) { +gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, i32 bi) { AsmBlock const *b = &cfg->blocks[bi]; AstAsmInstruction *last = cfg->insts[b->last]; - AsmInstructionFacts *lf = map_get(&acc->instruction_facts, last); + AsmInstructionFacts *lf = map_get(&cfg->instruction_facts, last); if (lf != nullptr && lf->branch_target != nullptr) { i32 *t = map_get(&cfg->label_block, lf->branch_target); @@ -184,23 +237,23 @@ gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, AsmMnemonicAccumulator } } bool terminal = (lf != nullptr) && lf->is_terminal; - if (!terminal && bi > cast(i32)cfg->blocks.count) { + if (!terminal && (bi+1 >= cast(i32)cfg->blocks.count)) { return true; // straight-line / conditional tail with nothing after it } return false; } template -gb_internal void check_asm_cfg_report_undef_reg(AsmCtx *asm_ctx, Entity *tmpl_entity, +gb_internal void check_asm_cfg_report_undef_reg(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *tmpl_entity, AstAsmInstruction *instr, String name, u16 bit) { char const *rname = asm_ctx->clobber_reg_bit_name(bit); String owner = {}; char const *role = nullptr; - for (auto const &ed : tmpl_entity->AsmTemplate.decls) { - if (ed.pin.len == 0 || ed.entity == nullptr) { - continue; - } - if (asm_ctx->clobber_bit_for_reg_name(ed.pin) != bit) { + + auto const &decls = tmpl_entity->AsmTemplate.decls; + for_array(i, decls) { + auto const &ed = decls[i]; + if (ed.entity == nullptr || cfg->decl_pin_bit[i] != bit) { continue; } if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) { @@ -228,15 +281,14 @@ gb_internal void check_asm_cfg_report_undef_reg(AsmCtx *asm_ctx, Entity *tmpl_en } template -gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *entity, AsmCfg *cfg, - AsmMnemonicAccumulator *acc) { +gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerContext *ctx, Entity *entity) { GB_ASSERT(entity->kind == Entity_AsmTemplate); auto const &decls = entity->AsmTemplate.decls; bool diverging = entity->type->Proc.diverging; if (cfg->blocks.count == 0) { // With an empty body, the CFG cannot really do nothing - if (diverging && !acc->saw_any_instructions) { + if (diverging && !cfg->saw_any_instructions) { error(entity->token, "This asm template is declared as diverging (-> !) but its body is empty and cannot diverge"); } return; @@ -248,40 +300,28 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent } u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED; - PtrMap entity_to_index = {}; - map_init(&entity_to_index); - defer (map_destroy(&entity_to_index)); - u64 universe_pm = 0; - for_array(i, decls) { - if (decls[i].entity != nullptr) { - map_set(&entity_to_index, decls[i].entity, cast(i32)i); - universe_pm |= (cast(u64)1 << i); - } - } + u64 const universe_pm = cfg->universe_pm; auto bit_of = [&](Entity *e) -> u64 { - i32 *ix = map_get(&entity_to_index, e); + i32 *ix = map_get(&cfg->entity_to_index, e); return ix ? (cast(u64)1 << *ix) : cast(u64)0; }; // NOTE(bill): entry seed intiailization which mirrors the linear seeding of defined_regs u16 seed_regs = 0; u64 seed_pm = 0; - for (auto const &ed : decls) { + for_array(i, decls) { + auto const &ed = decls[i]; + u16 pin_bit = cfg->decl_pin_bit[i]; if (ed.no_init) { seed_pm |= bit_of(ed.entity); - if (ed.pin.len != 0) { - seed_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); - } + seed_regs |= pin_bit; } switch (ed.param_group) { case AsmTemplateEntityDeclParamGroup_Input: seed_pm |= bit_of(ed.entity); - if (ed.pin.len != 0) { - seed_regs |= asm_ctx->clobber_bit_for_reg_name(ed.pin); - } + seed_regs |= pin_bit; break; case AsmTemplateEntityDeclParamGroup_Output: - // NOTE(bill): input provides the value if (ed.tie >= 0) { seed_pm |= bit_of(ed.entity); } @@ -327,7 +367,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent u64 gp = 0; AsmBlock const &b = cfg->blocks[bi]; for (i32 ii = b.first; ii <= b.last; ii++) { - AsmInstructionFacts *f = map_get(&acc->instruction_facts, cfg->insts[ii]); + AsmInstructionFacts *f = map_get(&cfg->instruction_facts, cfg->insts[ii]); if (f == nullptr) { continue; } @@ -444,7 +484,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent for (i32 ii = b.first; ii <= b.last; ii++) { AstAsmInstruction *instr = cfg->insts[ii]; - AsmInstructionFacts *f = map_get(&acc->instruction_facts, instr); + AsmInstructionFacts *f = map_get(&cfg->instruction_facts, instr); if (f == nullptr) { continue; } @@ -454,12 +494,12 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent if ((undef & bit) == 0) { continue; } - check_asm_cfg_report_undef_reg(asm_ctx, entity, instr, f->name, bit); + check_asm_cfg_report_undef_reg(asm_ctx, cfg, entity, instr, f->name, bit); reported_regs |= bit; } for (Entity *pe : f->read_params) { - i32 *ix = map_get(&entity_to_index, pe); + i32 *ix = map_get(&cfg->entity_to_index, pe); if (ix == nullptr) { continue; } @@ -489,7 +529,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent if (!cfg->blocks[bi].reachable) { continue; } - if (!check_asm_cfg_block_leaves(cfg, acc, cast(i32)bi)) { + if (!check_asm_cfg_block_leaves(cfg, cast(i32)bi)) { continue; } any_exit = true; @@ -499,7 +539,8 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent // NOTE(bill): Outputs must be assigned on every path that returns if (any_exit && !diverging) { - for (auto const &ed : decls) { + for_array(i, decls) { + auto const &ed = decls[i]; if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) { continue; } @@ -507,10 +548,10 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent continue; } - bool written; - if (ed.pin.len != 0) { - u16 bit = asm_ctx->clobber_bit_for_reg_name(ed.pin); - written = (bit != 0) && (exit_regs & bit) != 0; + bool written = false; + u16 bit = cfg->decl_pin_bit[i]; + if (bit != 0) { + written = (exit_regs & bit) != 0; } else { written = (exit_pm & bit_of(ed.entity)) != 0; } @@ -527,7 +568,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, CheckerContext *ctx, Ent if (diverging) { // No reachable path may return / fall off the end bool any_leak = false; for_array(bi, cfg->blocks) { - if (cfg->blocks[bi].reachable && check_asm_cfg_block_leaves(cfg, acc, cast(i32)bi)) { + if (cfg->blocks[bi].reachable && check_asm_cfg_block_leaves(cfg, cast(i32)bi)) { any_leak = true; break; } From a2d9ca86973c87d01afcb09298ba034d8b3d2d17 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 22:25:53 +0100 Subject: [PATCH 33/54] Remove unneeded hash maps when you can store the data directly on the nodes --- src/check_asm.cpp | 28 ++++++++++++++-------------- src/check_asm_cfg.cpp | 43 +++++++++++++++++++++++++------------------ src/check_expr.cpp | 4 ++++ src/parser.cpp | 1 + src/parser.hpp | 1 + 5 files changed, 45 insertions(+), 32 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 2b0fde8d7..1d5da9b02 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1121,11 +1121,11 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm name = asm_ctx->pseudo_mnemonic_strings[pseudo_mnemonic]; } - AsmInstructionFacts facts = {}; - facts.node = instr; - facts.name = name; - facts.gen_params.allocator = heap_allocator(); - facts.read_params.allocator = heap_allocator(); + AsmInstructionFacts *facts = gb_alloc_item(permanent_allocator(), AsmInstructionFacts); + facts->node = instr; + facts->name = name; + facts->gen_params.allocator = heap_allocator(); + facts->read_params.allocator = heap_allocator(); defer ({ for (auto const &op : operands) { @@ -1136,11 +1136,11 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm if (e == nullptr || e->kind != Entity_Label) { continue; } - facts.branch_target = e; + facts->branch_target = e; break; } - map_set(&cfg->instruction_facts, instr, facts); + instr->facts = facts; }); @@ -1541,7 +1541,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // Handle clobbering from mnemonic auto clobber = clobber_forms[valid_form_index]; - facts.read_regs = cast(u16)clobber.implicit_rd & asm_ctx->CLOBBER_REGS_NAMED; + facts->read_regs = cast(u16)clobber.implicit_rd & asm_ctx->CLOBBER_REGS_NAMED; // NOTE(bill): reads_mem/writes_mem are per-FORM capability bits. // A form with an r/m slot (e.g. add r/m32, imm32) carries them even @@ -1630,7 +1630,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm explicit_writes |= synth; } - facts.gen_regs = produced | pinned_param_writes; + facts->gen_regs = produced | pinned_param_writes; // NOTE(bill): mnemonics such as `xor r, r` / `sub r, r` act as zeroing the destination // independent of its prior value: the read is architecturally dead, so it must not count as a use. @@ -1665,10 +1665,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm } if (!self_zeroing && (cast(u16)clobber.read & (1u << slot))) { - array_add(&facts.read_params, pe); + array_add(&facts->read_params, pe); } if (cast(u16)clobber.written & (1u << slot)) { - array_add(&facts.gen_params, pe); + array_add(&facts->gen_params, pe); } } @@ -1700,9 +1700,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // A conditional branch reads a flag and can fall through -> not terminal. bool conditional = clobber.is_conditional(); - facts.is_control = control; - facts.is_conditional = conditional; - facts.is_terminal = halt || (control && !conditional); + facts->is_control = control; + facts->is_conditional = conditional; + facts->is_terminal = halt || (control && !conditional); } asm_ctx->clobber_implicit_regs(&tmpl_entity->AsmTemplate.clobber_registers_set, produced); diff --git a/src/check_asm_cfg.cpp b/src/check_asm_cfg.cpp index 8d4e4eb39..1f37ccb3d 100644 --- a/src/check_asm_cfg.cpp +++ b/src/check_asm_cfg.cpp @@ -44,11 +44,8 @@ struct AsmCfg { char const *impure_reason; Ast * impure_reason_node; - PtrMap instruction_facts; - Array insts; // program-order (only for fact-carrying instrs) Array blocks; - PtrMap label_block; // key: Entity_Label* PtrMap entity_to_index; Array decl_pin_bit; @@ -56,7 +53,6 @@ struct AsmCfg { }; gb_internal void asm_cfg_init(AsmCfg *cfg) { - map_init(&cfg->instruction_facts); map_init(&cfg->entity_to_index); cfg->decl_pin_bit.allocator = heap_allocator(); cfg->can_be_pure = true; @@ -71,12 +67,24 @@ gb_internal void asm_cfg_destroy(AsmCfg *cfg) { } array_free(&cfg->blocks); array_free(&cfg->insts); - map_destroy(&cfg->label_block); - map_destroy(&cfg->instruction_facts); map_destroy(&cfg->entity_to_index); array_free(&cfg->decl_pin_bit); } +gb_internal i32 asm_cfg_label_block_index(Entity *entity) { + if (entity != nullptr && entity->kind == Entity_Label) { + return entity->Label.asm_block_index; + } + return -1; +} +gb_internal bool asm_cfg_label_block_index_set(Entity *entity, i32 index) { + if (entity != nullptr && entity->kind == Entity_Label) { + GB_ASSERT(entity->Label.asm_block_index < 0); + entity->Label.asm_block_index = index; + } + return false; +} + // The physical-register bit a decl is pinned to. A width-view carries no pin of // its own; it inherits its source decl's pin. Returns 0 for unpinned decls. template @@ -124,7 +132,6 @@ gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, cfg->insts.allocator = heap_allocator(); cfg->blocks.allocator = heap_allocator(); - map_init(&cfg->label_block); bool need_leader = true; @@ -136,7 +143,7 @@ gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, // opens; consecutive labels share it. A trailing label maps to blocks.count. Entity *le = node->AsmLabelDecl.name->Ident.entity; if (le != nullptr) { - map_set(&cfg->label_block, le, cast(i32)cfg->blocks.count); + asm_cfg_label_block_index_set(le, cast(i32)cfg->blocks.count); } need_leader = true; continue; @@ -146,7 +153,7 @@ gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, } AstAsmInstruction *instr = &node->AsmInstruction; - AsmInstructionFacts *facts = map_get(&cfg->instruction_facts, instr); + AsmInstructionFacts *facts = instr->facts; // Prefixes and pseudo-macro ops (li/la) carry no facts and never branch. if (need_leader || cfg->blocks.count == 0) { @@ -175,16 +182,16 @@ gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, AsmBlock *b = &cfg->blocks[bi]; AstAsmInstruction *last = cfg->insts[b->last]; - AsmInstructionFacts *lf = map_get(&cfg->instruction_facts, last); + AsmInstructionFacts *lf = last->facts; i32 branch_succ = -1; bool fallthrough = true; if (lf != nullptr && lf->is_control) { if (lf->branch_target != nullptr) { - i32 *t = map_get(&cfg->label_block, lf->branch_target); - if (t != nullptr && *t < cast(i32)cfg->blocks.count) { - branch_succ = *t; // in-range internal target ('jmp .l' / 'jz .l') + i32 t = asm_cfg_label_block_index(lf->branch_target); + if (0 <= t && t < cast(i32)cfg->blocks.count) { + branch_succ = t; // in-range internal target ('jmp .l' / 'jz .l') } // For `t == blocks.count`, this implies a jump to the implicit end, and is handled as "leaves" below } @@ -228,11 +235,11 @@ gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, i32 bi) { AsmBlock const *b = &cfg->blocks[bi]; AstAsmInstruction *last = cfg->insts[b->last]; - AsmInstructionFacts *lf = map_get(&cfg->instruction_facts, last); + AsmInstructionFacts *lf = last->facts; if (lf != nullptr && lf->branch_target != nullptr) { - i32 *t = map_get(&cfg->label_block, lf->branch_target); - if (t != nullptr && *t >= cast(i32)cfg->blocks.count) { + i32 t = asm_cfg_label_block_index(lf->branch_target); + if (t >= 0 && t >= cast(i32)cfg->blocks.count) { return true; // 'jmp .end' — falls into the implicit return } } @@ -367,7 +374,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont u64 gp = 0; AsmBlock const &b = cfg->blocks[bi]; for (i32 ii = b.first; ii <= b.last; ii++) { - AsmInstructionFacts *f = map_get(&cfg->instruction_facts, cfg->insts[ii]); + AsmInstructionFacts *f = cfg->insts[ii]->facts; if (f == nullptr) { continue; } @@ -484,7 +491,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont for (i32 ii = b.first; ii <= b.last; ii++) { AstAsmInstruction *instr = cfg->insts[ii]; - AsmInstructionFacts *f = map_get(&cfg->instruction_facts, instr); + AsmInstructionFacts *f = instr->facts; if (f == nullptr) { continue; } diff --git a/src/check_expr.cpp b/src/check_expr.cpp index 091ebdac2..937a0eb07 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -13894,6 +13894,10 @@ gb_internal gbString write_expr_to_string(gbString str, Ast *node, bool shorthan str = gb_string_appendc(str, " = "); str = write_expr_to_string(str, spec->value, shorthand); } + for (Ast *dir : spec->directives) { + str = gb_string_appendc(str, " "); + str = write_expr_to_string(str, dir, shorthand); + } case_end; case_ast_node(clobber, AsmClobber, node); diff --git a/src/parser.cpp b/src/parser.cpp index f8ccb79a6..43fbea7c9 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -548,6 +548,7 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { case Ast_AsmInstruction: n->AsmInstruction.name = clone_ast(n->AsmInstruction.name, f); n->AsmInstruction.operands = clone_ast_array(n->AsmInstruction.operands, f); + n->AsmInstruction.facts = nullptr; break; case Ast_AsmMemoryOperand: n->AsmMemoryOperand.segment_override = clone_ast(n->AsmMemoryOperand.segment_override, f); diff --git a/src/parser.hpp b/src/parser.hpp index ad82834ed..260cb8a85 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -510,6 +510,7 @@ struct AstSplitArgs { u16 mnemonic; \ u8 suffix_flags; \ i32 valid_form_index; \ + struct AsmInstructionFacts *facts; \ }) \ AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ Token open; \ From 477fd7467bc9a39b199e69e0c7d30c41a187a69d Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 22:32:48 +0100 Subject: [PATCH 34/54] Ignore flag-pinned output --- src/check_asm_cfg.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/check_asm_cfg.cpp b/src/check_asm_cfg.cpp index 1f37ccb3d..b866e1b56 100644 --- a/src/check_asm_cfg.cpp +++ b/src/check_asm_cfg.cpp @@ -554,6 +554,9 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont if (ed.tie >= 0 || ed.no_init) { continue; } + if (ed.pin_flag.len != 0) { + continue; // flag-pinned output: defined by a flags side effect, not a reg/param write + } bool written = false; u16 bit = cfg->decl_pin_bit[i]; From 032566714c12f0f4d7d9fed400b0ab035a6c5dea Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 22:56:49 +0100 Subject: [PATCH 35/54] asm: correctly handle flags in the CFG --- .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 37 ++++-- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 21 ++++ src/asm_tables_amd64.cpp | 21 ++++ src/asm_tables_riscv.cpp | 37 ++++-- src/check_asm.cpp | 5 +- src/check_asm_cfg.cpp | 109 ++++++++++++------ 6 files changed, 175 insertions(+), 55 deletions(-) diff --git a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin index f4f70d9be..c19194c3c 100644 --- a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin @@ -120,12 +120,12 @@ main :: proc() { strings.write_string(&sb, "\n") strings.write_string(&sb, """ - enum ClobberFFlags : u8 { - ClobberFFlag_NV = 1<<0, // invalid operation - ClobberFFlag_DZ = 1<<1, // divide by zero - ClobberFFlag_OF = 1<<2, // overflow - ClobberFFlag_UF = 1<<3, // underflow - ClobberFFlag_NX = 1<<4, // inexact + enum ClobberFlags : u8 { + ClobberFlag_NV = 1<<0, // invalid operation + ClobberFlag_DZ = 1<<1, // divide by zero + ClobberFlag_OF = 1<<2, // overflow + ClobberFlag_UF = 1<<3, // underflow + ClobberFlag_NX = 1<<4, // inexact }; enum ClobberRegs : u8 { @@ -174,9 +174,28 @@ main :: proc() { return \"\"; } + u16 flags_from_name(String const &name) { + static const struct { String name; ClobberFlags flag; } table[] = { + // flags: accrued FP exception flags (fcsr[4:0]) + {str_lit(\"nx\"), ClobberFlag_NX}, // Inexact + {str_lit(\"uf\"), ClobberFlag_UF}, // Underflow + {str_lit(\"of\"), ClobberFlag_OF}, // Overflow + {str_lit(\"dz\"), ClobberFlag_DZ}, // Divide by Zero + {str_lit(\"nv\"), ClobberFlag_NV}, // Invalid Operation + }; + + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + + i32 flag_bit_from_name(String const &name, i32 *width_) { static const struct { String name; i32 bit; } table[] = { - // fflags: accrued FP exception flags (fcsr[4:0]) + // flags: accrued FP exception flags (fcsr[4:0]) {str_lit(\"nx\"), 0}, // Inexact {str_lit(\"uf\"), 1}, // Underflow {str_lit(\"of\"), 2}, // Overflow @@ -207,14 +226,14 @@ main :: proc() { OperandSet read; // operand slots whose register/CSR/mem-base is read ClobberRegs implicit_wr; // implicit reg writes (ra on C.JAL/C.JALR) ClobberRegs implicit_rd; // implicit reg reads (sp on the *SP forms) - ClobberFFlags fflags_wr; // accrued exception flags this op may raise + ClobberFlags flags_wr; // accrued exception flags this op may raise bool reads_frm; // consumes the dynamic rounding mode from fcsr bool writes_mem; bool reads_mem; SideEffectFlags side_effects; bool implies_clobber_flags() const { - return (fflags_wr != 0); + return (flags_wr != 0); } bool implies_clobber_memory() const { return writes_mem || reads_mem || diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index d64c6b2e4..558c8cd7e 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -237,6 +237,27 @@ main :: proc() { return \"\"; } + u16 flag_from_name(String const &name) { + static const struct {String name; ClobberFlags flag; } table[] = { + {str_lit(\"c\"), ClobberFlag_CF}, // Carry + {str_lit(\"p\"), ClobberFlag_PF}, // Parity + {str_lit(\"a\"), ClobberFlag_AF}, // Auxiliary Carry + {str_lit(\"z\"), ClobberFlag_ZF}, // Zero + {str_lit(\"s\"), ClobberFlag_SF}, // Sign + {str_lit(\"t\"), ClobberFlag_TF}, // Trap + {str_lit(\"i\"), ClobberFlag_IF}, // Interrupt Enable + {str_lit(\"d\"), ClobberFlag_DF}, // Direction + {str_lit(\"o\"), ClobberFlag_OF}, // Overflow + }; + + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + i32 flag_bit_from_name(String const &name, i32 *width_) { static const struct {String name; i32 bit; } table[] = { {str_lit(\"c\"), 0}, // Carry diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 4fd0d03e6..657204e90 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -240,6 +240,27 @@ struct Asm_amd64 { return ""; } + u16 flag_from_name(String const &name) { + static const struct {String name; ClobberFlags flag; } table[] = { + {str_lit("c"), ClobberFlag_CF}, // Carry + {str_lit("p"), ClobberFlag_PF}, // Parity + {str_lit("a"), ClobberFlag_AF}, // Auxiliary Carry + {str_lit("z"), ClobberFlag_ZF}, // Zero + {str_lit("s"), ClobberFlag_SF}, // Sign + {str_lit("t"), ClobberFlag_TF}, // Trap + {str_lit("i"), ClobberFlag_IF}, // Interrupt Enable + {str_lit("d"), ClobberFlag_DF}, // Direction + {str_lit("o"), ClobberFlag_OF}, // Overflow + }; + + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + i32 flag_bit_from_name(String const &name, i32 *width_) { static const struct {String name; i32 bit; } table[] = { {str_lit("c"), 0}, // Carry diff --git a/src/asm_tables_riscv.cpp b/src/asm_tables_riscv.cpp index 62fddbda9..a118314a1 100644 --- a/src/asm_tables_riscv.cpp +++ b/src/asm_tables_riscv.cpp @@ -68,12 +68,12 @@ struct Asm_riscv { }; - enum ClobberFFlags : u8 { - ClobberFFlag_NV = 1<<0, // invalid operation - ClobberFFlag_DZ = 1<<1, // divide by zero - ClobberFFlag_OF = 1<<2, // overflow - ClobberFFlag_UF = 1<<3, // underflow - ClobberFFlag_NX = 1<<4, // inexact + enum ClobberFlags : u8 { + ClobberFlag_NV = 1<<0, // invalid operation + ClobberFlag_DZ = 1<<1, // divide by zero + ClobberFlag_OF = 1<<2, // overflow + ClobberFlag_UF = 1<<3, // underflow + ClobberFlag_NX = 1<<4, // inexact }; enum ClobberRegs : u8 { @@ -122,9 +122,28 @@ struct Asm_riscv { return ""; } + u16 flags_from_name(String const &name) { + static const struct { String name; ClobberFlags flag; } table[] = { + // flags: accrued FP exception flags (fcsr[4:0]) + {str_lit("nx"), ClobberFlag_NX}, // Inexact + {str_lit("uf"), ClobberFlag_UF}, // Underflow + {str_lit("of"), ClobberFlag_OF}, // Overflow + {str_lit("dz"), ClobberFlag_DZ}, // Divide by Zero + {str_lit("nv"), ClobberFlag_NV}, // Invalid Operation + }; + + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + + i32 flag_bit_from_name(String const &name, i32 *width_) { static const struct { String name; i32 bit; } table[] = { - // fflags: accrued FP exception flags (fcsr[4:0]) + // flags: accrued FP exception flags (fcsr[4:0]) {str_lit("nx"), 0}, // Inexact {str_lit("uf"), 1}, // Underflow {str_lit("of"), 2}, // Overflow @@ -155,14 +174,14 @@ struct Asm_riscv { OperandSet read; // operand slots whose register/CSR/mem-base is read ClobberRegs implicit_wr; // implicit reg writes (ra on C.JAL/C.JALR) ClobberRegs implicit_rd; // implicit reg reads (sp on the *SP forms) - ClobberFFlags fflags_wr; // accrued exception flags this op may raise + ClobberFlags flags_wr; // accrued exception flags this op may raise bool reads_frm; // consumes the dynamic rounding mode from fcsr bool writes_mem; bool reads_mem; SideEffectFlags side_effects; bool implies_clobber_flags() const { - return (fflags_wr != 0); + return (flags_wr != 0); } bool implies_clobber_memory() const { return writes_mem || reads_mem || diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 1d5da9b02..3ed67ede8 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1630,7 +1630,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm explicit_writes |= synth; } - facts->gen_regs = produced | pinned_param_writes; + facts->gen_regs = produced | pinned_param_writes; + facts->gen_flags = cast(u16)clobber.flags_wr; // NOTE(bill): mnemonics such as `xor r, r` / `sub r, r` act as zeroing the destination // independent of its prior value: the read is architecturally dead, so it must not count as a use. @@ -2715,7 +2716,7 @@ gb_internal void check_asm_template_from_entity(CheckerContext *c, Entity *e, De if (build_context.metrics.arch == TargetArch_amd64) { check_asm_template(&g_asm_amd64, c, e, d); } else if (build_context.metrics.arch == TargetArch_riscv64) { - check_asm_template(&g_asm_riscv, c, e, d); + // check_asm_template(&g_asm_riscv, c, e, d); } else { error(e->token, "asm templates are not currently supported for this target"); } diff --git a/src/check_asm_cfg.cpp b/src/check_asm_cfg.cpp index b866e1b56..3b55de62a 100644 --- a/src/check_asm_cfg.cpp +++ b/src/check_asm_cfg.cpp @@ -1,10 +1,16 @@ struct AsmBlock { i32 first, last; Array succs; + u16 in_defs; u16 out_defs; + + u16 in_flags; + u16 out_flags; + PtrSet in_params; PtrSet out_params; + bool reachable; }; @@ -12,6 +18,7 @@ struct AsmInstructionFacts { AstAsmInstruction *node; String name; + u16 gen_flags; // flag bits this instruction defines u16 gen_regs; u16 read_regs; @@ -105,6 +112,15 @@ gb_internal u16 asm_decl_resolve_pin_bit(AsmCtx *asm_ctx, Array +gb_internal u16 asm_decl_resolve_flag_bit(AsmCtx *asm_ctx, AsmTemplateEntityDecl const &ed) { + if (ed.pin_flag.len == 0) { + return 0; + } + auto flags = asm_ctx->flag_from_name(ed.pin_flag); + return cast(u16)flags; +} + template gb_internal void asm_cfg_populate_decls(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *entity) { auto const &decls = entity->AsmTemplate.decls; @@ -305,7 +321,8 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont error(entity->token, "'asm' templates cannot have more than 64 total parameter declarations, got %td", decls.count); return; } - u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED; + u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED; + u16 const FLAG_TOP = cast(u16)~cast(u16)0; u64 const universe_pm = cfg->universe_pm; auto bit_of = [&](Entity *e) -> u64 { @@ -338,12 +355,15 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont isize const n = cfg->blocks.count; - auto in_regs = slice_make(heap_allocator(), n); defer (slice_free(&in_regs, heap_allocator())); - auto out_regs = slice_make(heap_allocator(), n); defer (slice_free(&out_regs, heap_allocator())); - auto gen_regs = slice_make(heap_allocator(), n); defer (slice_free(&gen_regs, heap_allocator())); - auto in_pm = slice_make(heap_allocator(), n); defer (slice_free(&in_pm, heap_allocator())); - auto out_pm = slice_make(heap_allocator(), n); defer (slice_free(&out_pm, heap_allocator())); - auto gen_pm = slice_make(heap_allocator(), n); defer (slice_free(&gen_pm, heap_allocator())); + auto in_regs = slice_make(heap_allocator(), n); defer (slice_free(&in_regs, heap_allocator())); + auto out_regs = slice_make(heap_allocator(), n); defer (slice_free(&out_regs, heap_allocator())); + auto gen_regs = slice_make(heap_allocator(), n); defer (slice_free(&gen_regs, heap_allocator())); + auto in_flags = slice_make(heap_allocator(), n); defer (slice_free(&in_flags, heap_allocator())); + auto out_flags = slice_make(heap_allocator(), n); defer (slice_free(&out_flags, heap_allocator())); + auto gen_flags = slice_make(heap_allocator(), n); defer (slice_free(&gen_flags, heap_allocator())); + auto in_pm = slice_make(heap_allocator(), n); defer (slice_free(&in_pm, heap_allocator())); + auto out_pm = slice_make(heap_allocator(), n); defer (slice_free(&out_pm, heap_allocator())); + auto gen_pm = slice_make(heap_allocator(), n); defer (slice_free(&gen_pm, heap_allocator())); // predecessors, restricted to reachable blocks auto preds = slice_make>(heap_allocator(), n); @@ -371,6 +391,7 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont for_array(bi, cfg->blocks) { u16 gr = 0; + u16 gf = 0; u64 gp = 0; AsmBlock const &b = cfg->blocks[bi]; for (i32 ii = b.first; ii <= b.last; ii++) { @@ -379,12 +400,14 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont continue; } gr |= f->gen_regs; + gf |= f->gen_flags; for (Entity *pe : f->gen_params) { gp |= bit_of(pe); } } - gen_regs[bi] = gr; - gen_pm[bi] = gp; + gen_regs[bi] = gr; + gen_flags[bi] = gf; + gen_pm[bi] = gp; } // NOTE(bill): initialize the blocks @@ -394,14 +417,17 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont continue; } if (bi == 0) { - in_regs[bi] = seed_regs; - in_pm[bi] = seed_pm; + in_regs[bi] = seed_regs; + in_pm[bi] = seed_pm; + in_flags[bi] = 0; // no flag is defined at the template entry point } else { - in_regs[bi] = REG_TOP; - in_pm[bi] = universe_pm; + in_regs[bi] = REG_TOP; + in_pm[bi] = universe_pm; + in_flags[bi] = FLAG_TOP; } - out_regs[bi] = in_regs[bi] | gen_regs[bi]; - out_pm[bi] = in_pm[bi] | gen_pm[bi]; + out_regs[bi] = in_regs[bi] | gen_regs[bi]; + out_pm[bi] = in_pm[bi] | gen_pm[bi]; + out_flags[bi] = in_flags[bi] | gen_flags[bi]; } // forward must-analysis: in = AND(preds.out); out = in | gen. Iterate to fixpoint. @@ -414,26 +440,34 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont } u16 nin_r = seed_regs; + u16 nin_f = 0; u64 nin_p = seed_pm; if (bi != 0) { nin_r = REG_TOP; + nin_f = FLAG_TOP; nin_p = universe_pm; for (i32 p : preds[bi]) { - nin_r &= out_regs[p]; - nin_p &= out_pm[p]; + nin_r &= out_regs[p]; + nin_r &= out_flags[p]; + nin_p &= out_pm[p]; } } u16 nout_r = nin_r | gen_regs[bi]; u64 nout_p = nin_p | gen_pm[bi]; + u16 nout_f = nin_f | gen_flags[bi]; if (nin_r != in_regs[bi] || nin_p != in_pm[bi] || + nin_f != in_flags[bi] || nout_r != out_regs[bi] || - nout_p != out_pm[bi]) { - in_regs[bi] = nin_r; - in_pm[bi] = nin_p; - out_regs[bi] = nout_r; - out_pm[bi] = nout_p; + nout_p != out_pm[bi] || + nout_f != out_flags[bi]) { + in_regs[bi] = nin_r; + in_pm[bi] = nin_p; + in_flags[bi] = nin_f; + out_regs[bi] = nout_r; + out_pm[bi] = nout_p; + out_flags[bi] = nout_f; changed = true; } } @@ -442,8 +476,10 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont // NOTE(bill): publish the register masks and materialise the parameter sets onto the blocks for_array(bi, cfg->blocks) { AsmBlock *b = &cfg->blocks[bi]; - b->in_defs = in_regs[bi]; - b->out_defs = out_regs[bi]; + b->in_defs = in_regs[bi]; + b->out_defs = out_regs[bi]; + b->in_flags = in_flags[bi]; + b->out_flags = out_flags[bi]; if (!b->reachable) { continue; } @@ -529,8 +565,9 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont } { // NOTE(bill): Collect the template's return points reachable blocks that leave via the end - u16 exit_regs = REG_TOP; - u64 exit_pm = universe_pm; + u16 exit_regs = REG_TOP; + u64 exit_pm = universe_pm; + u16 exit_flags = FLAG_TOP; bool any_exit = false; for_array(bi, cfg->blocks) { if (!cfg->blocks[bi].reachable) { @@ -540,8 +577,9 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont continue; } any_exit = true; - exit_regs &= out_regs[bi]; - exit_pm &= out_pm[bi]; + exit_regs &= out_regs[bi]; + exit_pm &= out_pm[bi]; + exit_flags &= out_flags[bi]; } // NOTE(bill): Outputs must be assigned on every path that returns @@ -554,17 +592,18 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont if (ed.tie >= 0 || ed.no_init) { continue; } - if (ed.pin_flag.len != 0) { - continue; // flag-pinned output: defined by a flags side effect, not a reg/param write - } bool written = false; - u16 bit = cfg->decl_pin_bit[i]; - if (bit != 0) { - written = (exit_regs & bit) != 0; + u16 flag_bit = asm_decl_resolve_flag_bit(asm_ctx, ed); + u16 reg_bit = cfg->decl_pin_bit[i]; + if (flag_bit != 0) { + // Flag-pinned output: defined iff the pinned flag is set on every returning path. + written = (exit_flags & flag_bit) != 0; + } else if (reg_bit != 0) { + written = (exit_regs & reg_bit) != 0; } else { written = (exit_pm & bit_of(ed.entity)) != 0; - } + } if (!written) { error(ed.entity->token, "'asm' output parameter '%.*s' is not assigned on all paths through this template; " From a9068261bfd45aa2cb8a5d969ac91c0f0697d197 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 23:12:38 +0100 Subject: [PATCH 36/54] Fix view-width testing for unpinned parameters in the lattice --- src/check_asm.cpp | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 3ed67ede8..b81864bc1 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1671,6 +1671,34 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm if (cast(u16)clobber.written & (1u << slot)) { array_add(&facts->gen_params, pe); } + + + { // View aliasing: a view decl shares its source's physical register. + auto const &decls = tmpl_entity->AsmTemplate.decls; + i32 di = -1; + check_asm_find_group(pe, decls, &di); + if (di >= 0 && decls[di].view_of >= 0) { + i32 src_i = decls[di].view_of; + Entity *src_e = decls[src_i].entity; + if (src_e != nullptr) { + GB_ASSERT_MSG(asm_decl_resolve_pin_bit(asm_ctx, decls, cast(i32)di) == 0 && + asm_decl_resolve_pin_bit(asm_ctx, decls, src_i) == 0, + "view/source share a reg bit; fix the width gate on the reg-bit path, not gen_params"); + + // A read of the view is a read of the source + if (cast(u16)clobber.read & (1u << slot)) { + array_add(&facts->read_params, src_e); + } + // A write of the view defines the source only if it covers the parent + if (cast(u16)clobber.written & (1u << slot)) { + i32 parent_w = check_asm_operand_bit_width(src_e->type); + if (decls[di].view_bits == 32 || decls[di].view_bits == parent_w) { + array_add(&facts->gen_params, src_e); + } + } + } + } + } } { From e093329012f0cf39afc16a0f72b5c81f1b126f5f Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 24 Aug 2026 23:35:41 +0100 Subject: [PATCH 37/54] asm: add a backward liveness check for the CFG --- src/check_asm.cpp | 40 ++++++++---- src/check_asm_cfg.cpp | 140 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 166 insertions(+), 14 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index b81864bc1..c03b081fd 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1107,7 +1107,7 @@ gb_internal void check_operand_constraints(AsmCtx *asm_ctx, Slice const } template -gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, +gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, u16 mnemonic, u16 pseudo_mnemonic, Slice const &operands, u8 previous_prefix, Ast *previous_prefix_instr, AsmCfg *cfg) { @@ -1514,7 +1514,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm error(instr->name, "The asm instruction '%.*s' expects %d..=%d operands, got %td", LIT(name), min_count, max_count, operands.count); } print_possible_forms(); - return; + return false; } if (matched) { @@ -1687,8 +1687,20 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // A read of the view is a read of the source if (cast(u16)clobber.read & (1u << slot)) { - array_add(&facts->read_params, src_e); + i32 di = -1; + for_array(k, decls) { + if (decls[k].entity == pe) { + di = cast(i32)k; + break; + } + } + if (di >= 0 && decls[di].view_of >= 0 && decls[decls[di].view_of].entity != nullptr) { + array_add(&facts->read_params, decls[decls[di].view_of].entity); + } else { + array_add(&facts->read_params, pe); + } } + // A write of the view defines the source only if it covers the parent if (cast(u16)clobber.written & (1u << slot)) { i32 parent_w = check_asm_operand_bit_width(src_e->type); @@ -1766,8 +1778,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm cfg->impure_reason = why; cfg->impure_reason_node = instr->name; } + + // NOTE(bill): return true even on a purity test because the instruction is still good } - return; + return true; } // NOTE(bill): Failure path @@ -1878,6 +1892,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm print_possible_forms(); } end_error_block(); + + return false; } @@ -2461,6 +2477,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity u8 previous_prefix = 0; Ast *previous_prefix_instr = nullptr; // for a good error location + bool all_instructions_good = true; for (Ast *instruction_ : at->instructions) { switch (instruction_->kind) { @@ -2489,9 +2506,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity previous_prefix_instr = instruction_; } else if (res == CheckMnemomic_Mnemonic) { instr->suffix_flags = suffix_flags; - check_mnemonic(asm_ctx, ctx, entity, instr, mnemonic, 0, slice_from_array(operands), - previous_prefix, previous_prefix_instr, - &cfg); + all_instructions_good &= check_mnemonic(asm_ctx, ctx, entity, instr, mnemonic, 0, slice_from_array(operands), + previous_prefix, previous_prefix_instr, + &cfg); cfg.saw_any_instructions = true; @@ -2503,9 +2520,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity u16 pseudo_mnemonic = cast(u16)mnemonic; auto alias = asm_ctx->pseudo_alias(cast(u16)pseudo_mnemonic); u16 target_mnemonic = cast(u16)alias.target; - check_mnemonic(asm_ctx, ctx, entity, instr, target_mnemonic, pseudo_mnemonic, slice_from_array(operands), - previous_prefix, previous_prefix_instr, - &cfg); + all_instructions_good &=check_mnemonic(asm_ctx, ctx, entity, instr, target_mnemonic, pseudo_mnemonic, slice_from_array(operands), + previous_prefix, previous_prefix_instr, + &cfg); cfg.saw_any_instructions = true; @@ -2513,7 +2530,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity previous_prefix_instr = nullptr; } else if (res == CheckMnemomic_PseudoMacroMnemonic) { instr->suffix_flags = suffix_flags; - check_pseudo_macro_mnemonic(asm_ctx, entity, instr, slice_from_array(operands)); + all_instructions_good &= check_pseudo_macro_mnemonic(asm_ctx, entity, instr, slice_from_array(operands)); cfg.saw_any_instructions = true; @@ -2627,6 +2644,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity check_asm_cfg_build(asm_ctx, &cfg, d->init_expr, entity); check_asm_cfg_analyse(asm_ctx, &cfg, ctx, entity); + check_asm_cfg_liveness(asm_ctx, &cfg, entity, /*emit_dead_writes*/all_instructions_good); bool vet_unused = false; { diff --git a/src/check_asm_cfg.cpp b/src/check_asm_cfg.cpp index 3b55de62a..3cee17560 100644 --- a/src/check_asm_cfg.cpp +++ b/src/check_asm_cfg.cpp @@ -8,6 +8,9 @@ struct AsmBlock { u16 in_flags; u16 out_flags; + u16 live_in_regs; + u16 live_out_regs; + PtrSet in_params; PtrSet out_params; @@ -134,8 +137,18 @@ gb_internal void asm_cfg_populate_decls(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *en Entity *e = decls[i].entity; cfg->decl_pin_bit[i] = asm_decl_resolve_pin_bit(asm_ctx, decls, cast(i32)i); if (e != nullptr) { - map_set(&cfg->entity_to_index, e, cast(i32)i); - cfg->universe_pm |= (cast(u64)1 << i); + if (decls[i].view_of >= 0) { + // NOTE(bill): A view shares its source's lattice bit, as it is not an independent value. + i32 src_i = decls[i].view_of; + Entity *src_e = decls[src_i].entity; + if (src_e != nullptr) { + map_set(&cfg->entity_to_index, e, src_i); // view entity -> source index + } + // NOTE(bill): No need to set a universe bit for the view as the source already has one + } else { + map_set(&cfg->entity_to_index, e, cast(i32)i); + cfg->universe_pm |= (cast(u64)1 << i); + } } } } @@ -549,8 +562,14 @@ gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerCont if (((run_pm >> *ix) & 1) == 0 && !ptr_set_exists(&reported_params, pe)) { Ast *loc = instr->name; for (Ast *op : instr->operands) { - if (entity_of_node(op) == pe) { loc = op; break; } + if (entity_of_node(op) == pe) { + loc = op; + break; + } } + gb_printf_err("RBW-ERROR site=