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Add missing x86 instructions
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gingerBill committed
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@@ -1307,4 +1307,82 @@ Mnemonic :: enum u16 {
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MOVBE,
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RDRAND,
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RDSEED,
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// -------------------------------------------------------------------------
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// SECTION: 4.28 Additional System / GPR Instructions
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// -------------------------------------------------------------------------
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SWAPGS,
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MONITOR,
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MWAIT,
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CLAC,
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STAC,
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RDFSBASE,
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RDGSBASE,
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WRFSBASE,
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WRGSBASE,
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PTWRITE,
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RDPID,
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WBNOINVD,
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SERIALIZE,
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PREFETCH,
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// -------------------------------------------------------------------------
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// SECTION: 4.29 WAITPKG Instructions
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// -------------------------------------------------------------------------
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TPAUSE,
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UMONITOR,
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UMWAIT,
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// -------------------------------------------------------------------------
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// SECTION: 4.30 Direct Store / Enqueue Store Instructions
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// -------------------------------------------------------------------------
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MOVDIRI,
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MOVDIR64B,
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ENQCMD,
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ENQCMDS,
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// -------------------------------------------------------------------------
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// SECTION: 4.31 Remote Atomic Operations (RAO-INT)
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// -------------------------------------------------------------------------
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AADD,
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AAND,
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AOR,
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AXOR,
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// -------------------------------------------------------------------------
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// SECTION: 4.32 Restricted Transactional Memory (RTM)
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// -------------------------------------------------------------------------
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XEND,
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XTEST,
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// -------------------------------------------------------------------------
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// SECTION: 4.33 AMD SVM (Secure Virtual Machine) Instructions
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// -------------------------------------------------------------------------
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VMRUN,
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VMMCALL,
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VMLOAD,
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VMSAVE,
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STGI,
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CLGI,
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SKINIT,
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INVLPGA,
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INVLPGB,
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TLBSYNC,
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// -------------------------------------------------------------------------
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// SECTION: 4.34 AMD SEV-SNP Instructions
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// -------------------------------------------------------------------------
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PVALIDATE,
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RMPADJUST,
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RMPUPDATE,
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PSMASH,
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// -------------------------------------------------------------------------
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// SECTION: 4.35 AMD Miscellaneous Instructions
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// -------------------------------------------------------------------------
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CLZERO,
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MONITORX,
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MWAITX,
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RDPRU,
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MCOMMIT,
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}
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@@ -4870,4 +4870,167 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{
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{written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}},
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{written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}},
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},
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// 8.23 Additional System / GPR Encodings
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.SWAPGS = { // privileged; swaps GS.base with IA32_KERNEL_GS_BASE
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{side_effects={.PRIVILEGED}},
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},
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.MONITOR = { // arms address monitor for [rAX]; ECX=extensions, EDX=hints
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{implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true},
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},
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.MWAIT = { // EAX=hints, ECX=extensions; enters optimized wait
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{implicit_rd={.RAX, .RCX}, side_effects={.HALT}},
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},
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.CLAC = { // clears EFLAGS.AC (not modeled in Clobber_Flags); CPL0
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{side_effects={.PRIVILEGED}},
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},
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.STAC = { // sets EFLAGS.AC (not modeled in Clobber_Flags); CPL0
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{side_effects={.PRIVILEGED}},
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},
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.RDFSBASE = {
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{written={0}},
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{written={0}},
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},
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.RDGSBASE = {
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{written={0}},
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{written={0}},
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},
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.WRFSBASE = {
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{read={0}},
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{read={0}},
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},
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.WRGSBASE = {
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{read={0}},
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{read={0}},
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},
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.PTWRITE = { // writes source to a PT trace packet; no flags
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{read={0}, reads_mem=true},
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{read={0}, reads_mem=true},
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},
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.RDPID = { // dest <- IA32_TSC_AUX
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{written={0}},
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},
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.WBNOINVD = { // privileged; writes back caches without invalidation
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{side_effects={.SERIALIZING, .PRIVILEGED}},
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},
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.SERIALIZE = { // serializes execution; no register/flag clobber
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{side_effects={.SERIALIZING}},
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},
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.PREFETCH = { // cache hint; no register or flag clobber
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{read={0}, reads_mem=true, side_effects={.HINT}},
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},
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// 8.24 WAITPKG Encodings
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.TPAUSE = { // reads control r32 + EDX:EAX deadline; CF <- result
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{read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}},
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},
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.UMONITOR = { // arms address monitor for [reg]
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{read={0}, reads_mem=true},
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},
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.UMWAIT = { // reads control r32 + EDX:EAX deadline; CF <- result
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{read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}},
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},
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// 8.25 Direct Store / Enqueue Store Encodings
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.MOVDIRI = { // direct store of source register to memory
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{read={0, 1}, writes_mem=true},
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{read={0, 1}, writes_mem=true},
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},
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.MOVDIR64B = { // 64-byte direct store: reads m512, writes [reg]
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{read={0}, implicit_rd={.RAX}, reads_mem=true, writes_mem=true},
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},
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.ENQCMD = { // enqueue store: reads m512, writes to device [reg]; ZF <- status
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{read={0}, reads_mem=true, writes_mem=true, flags_wr={.ZF}},
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},
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.ENQCMDS = { // supervisor enqueue store; ZF <- status
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{read={0}, reads_mem=true, writes_mem=true, flags_wr={.ZF}},
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},
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// 8.26 Remote Atomic Operation (RAO-INT) Encodings
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.AADD = { // atomic [mem] += reg; no flags, no result loaded
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{read={0, 1}, writes_mem=true, reads_mem=true},
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{read={0, 1}, writes_mem=true, reads_mem=true},
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},
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.AAND = { // atomic [mem] &= reg
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{read={0, 1}, writes_mem=true, reads_mem=true},
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{read={0, 1}, writes_mem=true, reads_mem=true},
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},
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.AOR = { // atomic [mem] |= reg
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{read={0, 1}, writes_mem=true, reads_mem=true},
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{read={0, 1}, writes_mem=true, reads_mem=true},
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},
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.AXOR = { // atomic [mem] ^= reg
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{read={0, 1}, writes_mem=true, reads_mem=true},
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{read={0, 1}, writes_mem=true, reads_mem=true},
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},
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// 8.27 Restricted Transactional Memory (RTM) Encodings
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.XEND = { // commits transaction; may transfer control on abort
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{side_effects={.CONTROL}},
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},
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.XTEST = { // ZF <- (not in transactional region)
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{flags_wr={.ZF}},
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},
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// 8.28 AMD SVM Encodings
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.VMRUN = { // privileged; runs guest from VMCB at [rAX]
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{implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}},
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},
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.VMMCALL = { // guest-to-hypervisor call
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{side_effects={.PRIVILEGED}},
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},
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.VMLOAD = { // privileged; loads guest state from VMCB at [rAX]
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{implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}},
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},
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.VMSAVE = { // privileged; saves guest state to VMCB at [rAX]
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{implicit_rd={.RAX}, writes_mem=true, side_effects={.PRIVILEGED}},
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},
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.STGI = { // privileged; sets global interrupt flag
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{side_effects={.PRIVILEGED}},
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},
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.CLGI = { // privileged; clears global interrupt flag
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{side_effects={.PRIVILEGED}},
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},
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.SKINIT = { // privileged; secure init from SLB at EAX
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{implicit_rd={.RAX}, side_effects={.PRIVILEGED}},
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},
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.INVLPGA = { // privileged; invalidates TLB entry [rAX] for ASID ECX
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{implicit_rd={.RAX, .RCX}, side_effects={.PRIVILEGED}},
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},
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.INVLPGB = { // privileged; rAX=va, ECX=count, EDX=flags
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{implicit_rd={.RAX, .RCX, .RDX}, side_effects={.PRIVILEGED}},
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},
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.TLBSYNC = { // privileged; synchronizes broadcast TLB invalidations
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{side_effects={.PRIVILEGED}},
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},
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// 8.29 AMD SEV-SNP Encodings
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.PVALIDATE = { // rAX=addr, ECX=size, EDX=validate; EAX<-rc, flags set
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{implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true},
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},
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.RMPADJUST = { // privileged; rAX=addr, RCX=attrs, RDX=level; EAX<-rc
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{implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}},
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},
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.RMPUPDATE = { // privileged; rAX=addr, RCX=ptr to RMP state; EAX<-rc
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{implicit_wr={.RAX}, implicit_rd={.RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, writes_mem=true, side_effects={.PRIVILEGED}},
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},
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.PSMASH = { // privileged; rAX=addr; EAX<-rc; splits 2M RMP entry
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{implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, side_effects={.PRIVILEGED}},
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},
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// 8.30 AMD Miscellaneous Encodings
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.CLZERO = { // zeroes the cache line at [rAX]
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{implicit_rd={.RAX}, writes_mem=true, side_effects={.CACHE}},
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},
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.MONITORX = { // arms address monitor for [rAX] with timer (EBX)
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{implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true},
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},
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.MWAITX = { // EAX=hints, ECX=extensions, EBX=timer; enters wait
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{implicit_rd={.RAX, .RCX, .RBX}, side_effects={.HALT}},
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},
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.RDPRU = { // ECX selects register; EDX:EAX <- value
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{implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}},
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},
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.MCOMMIT = { // commits pending stores; CF <- error status
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{flags_wr={.CF}, side_effects={.FENCE}},
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},
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}
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@@ -4917,4 +4917,183 @@ ENCODING_TABLE := [Mnemonic][]Encoding{
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{.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}},
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{.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}},
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},
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// -------------------------------------------------------------------------
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// SECTION: 8.23 Additional System / GPR Encodings
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// -------------------------------------------------------------------------
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.SWAPGS = { // 0F 01 F8
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{.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF8, {esc=._0F}},
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},
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.MONITOR = { // 0F 01 C8
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{.MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC8, {esc=._0F}},
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},
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.MWAIT = { // 0F 01 C9
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{.MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC9, {esc=._0F}},
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},
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.CLAC = { // 0F 01 CA
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{.CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCA, {esc=._0F}},
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},
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.STAC = { // 0F 01 CB
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{.STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCB, {esc=._0F}},
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},
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.RDFSBASE = { // F3 0F AE /0
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{.RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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{.RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}},
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},
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.RDGSBASE = { // F3 0F AE /1
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{.RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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{.RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}},
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},
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.WRFSBASE = { // F3 0F AE /2
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{.WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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{.WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}},
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},
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.WRGSBASE = { // F3 0F AE /3
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{.WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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{.WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}},
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},
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.PTWRITE = { // F3 0F AE /4
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{.PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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{.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}},
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},
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.RDPID = { // F3 0F C7 /7 (r64 in 64-bit mode, no REX.W)
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{.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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},
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.WBNOINVD = { // F3 0F 09
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{.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=PREFIX_F3}},
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},
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.SERIALIZE = { // NP 0F 01 E8
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{.SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xE8, {esc=._0F}},
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},
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.PREFETCH = { // 0F 0D /0
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{.PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 0, {esc=._0F, modrm_reg_ext=true}},
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},
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// -------------------------------------------------------------------------
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// SECTION: 8.24 WAITPKG Encodings
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// -------------------------------------------------------------------------
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.TPAUSE = { // 66 0F AE /6
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{.TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_66}},
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},
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.UMONITOR = { // F3 0F AE /6
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{.UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}},
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},
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.UMWAIT = { // F2 0F AE /6
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{.UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F2}},
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},
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// -------------------------------------------------------------------------
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// SECTION: 8.25 Direct Store / Enqueue Store Encodings
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// -------------------------------------------------------------------------
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.MOVDIRI = { // NP 0F 38 F9 /r (store r -> m)
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{.MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38}},
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{.MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, force_rex_w=true}},
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},
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.MOVDIR64B = { // 66 0F 38 F8 /r (r=dest addr, m512=src)
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{.MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_66}},
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},
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.ENQCMD = { // F2 0F 38 F8 /r
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{.ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F2}},
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},
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.ENQCMDS = { // F3 0F 38 F8 /r
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{.ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F3}},
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},
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// -------------------------------------------------------------------------
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// SECTION: 8.26 Remote Atomic Operation (RAO-INT) Encodings
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// -------------------------------------------------------------------------
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.AADD = { // NP 0F 38 FC /r
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{.AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38}},
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{.AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, force_rex_w=true}},
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},
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.AAND = { // 66 0F 38 FC /r
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{.AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66}},
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{.AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}},
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},
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.AOR = { // F2 0F 38 FC /r
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{.AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2}},
|
||||
{.AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}},
|
||||
},
|
||||
.AXOR = { // F3 0F 38 FC /r
|
||||
{.AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3}},
|
||||
{.AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3, force_rex_w=true}},
|
||||
},
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// SECTION: 8.27 Restricted Transactional Memory (RTM) Encodings
|
||||
// -------------------------------------------------------------------------
|
||||
.XEND = { // NP 0F 01 D5
|
||||
{.XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD5, {esc=._0F}},
|
||||
},
|
||||
.XTEST = { // NP 0F 01 D6
|
||||
{.XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD6, {esc=._0F}},
|
||||
},
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// SECTION: 8.28 AMD SVM Encodings
|
||||
// -------------------------------------------------------------------------
|
||||
.VMRUN = { // 0F 01 D8
|
||||
{.VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD8, {esc=._0F}},
|
||||
},
|
||||
.VMMCALL = { // 0F 01 D9
|
||||
{.VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD9, {esc=._0F}},
|
||||
},
|
||||
.VMLOAD = { // 0F 01 DA
|
||||
{.VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDA, {esc=._0F}},
|
||||
},
|
||||
.VMSAVE = { // 0F 01 DB
|
||||
{.VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDB, {esc=._0F}},
|
||||
},
|
||||
.STGI = { // 0F 01 DC
|
||||
{.STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDC, {esc=._0F}},
|
||||
},
|
||||
.CLGI = { // 0F 01 DD
|
||||
{.CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDD, {esc=._0F}},
|
||||
},
|
||||
.SKINIT = { // 0F 01 DE
|
||||
{.SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDE, {esc=._0F}},
|
||||
},
|
||||
.INVLPGA = { // 0F 01 DF
|
||||
{.INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDF, {esc=._0F}},
|
||||
},
|
||||
.INVLPGB = { // NP 0F 01 FE
|
||||
{.INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F}},
|
||||
},
|
||||
.TLBSYNC = { // NP 0F 01 FF
|
||||
{.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F}},
|
||||
},
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// SECTION: 8.29 AMD SEV-SNP Encodings
|
||||
// -------------------------------------------------------------------------
|
||||
.PVALIDATE = { // F2 0F 01 FF
|
||||
{.PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F2}},
|
||||
},
|
||||
.RMPADJUST = { // F3 0F 01 FE
|
||||
{.RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F3}},
|
||||
},
|
||||
.RMPUPDATE = { // F2 0F 01 FE
|
||||
{.RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F2}},
|
||||
},
|
||||
.PSMASH = { // F3 0F 01 FF
|
||||
{.PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F3}},
|
||||
},
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// SECTION: 8.30 AMD Miscellaneous Encodings
|
||||
// -------------------------------------------------------------------------
|
||||
.CLZERO = { // 0F 01 FC
|
||||
{.CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFC, {esc=._0F}},
|
||||
},
|
||||
.MONITORX = { // NP 0F 01 FA
|
||||
{.MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F}},
|
||||
},
|
||||
.MWAITX = { // NP 0F 01 FB
|
||||
{.MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFB, {esc=._0F}},
|
||||
},
|
||||
.RDPRU = { // 0F 01 FD
|
||||
{.RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFD, {esc=._0F}},
|
||||
},
|
||||
.MCOMMIT = { // F3 0F 01 FA
|
||||
{.MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F, prefix=PREFIX_F3}},
|
||||
},
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -8,7 +8,7 @@ package rexcode_x86_generated
|
||||
import lib "../.."
|
||||
|
||||
@(rodata)
|
||||
ENCODE_FORMS := [2395]lib.Encoding{
|
||||
ENCODE_FORMS := [2451]lib.Encoding{
|
||||
// .MOV
|
||||
{.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {explicit_count=2}},
|
||||
{.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {explicit_count=2}},
|
||||
@@ -3595,10 +3595,112 @@ ENCODE_FORMS := [2395]lib.Encoding{
|
||||
{.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .SWAPGS
|
||||
{.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 248, {esc=._0F}},
|
||||
// .MONITOR
|
||||
{.MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 200, {esc=._0F}},
|
||||
// .MWAIT
|
||||
{.MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 201, {esc=._0F}},
|
||||
// .CLAC
|
||||
{.CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 202, {esc=._0F}},
|
||||
// .STAC
|
||||
{.STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 203, {esc=._0F}},
|
||||
// .RDFSBASE
|
||||
{.RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .RDGSBASE
|
||||
{.RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .WRFSBASE
|
||||
{.WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .WRGSBASE
|
||||
{.WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .PTWRITE
|
||||
{.PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
{.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .RDPID
|
||||
{.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .WBNOINVD
|
||||
{.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=2}},
|
||||
// .SERIALIZE
|
||||
{.SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 232, {esc=._0F}},
|
||||
// .PREFETCH
|
||||
{.PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .TPAUSE
|
||||
{.TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .UMONITOR
|
||||
{.UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .UMWAIT
|
||||
{.UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=3, modrm_reg_ext=true, explicit_count=1}},
|
||||
// .MOVDIRI
|
||||
{.MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, explicit_count=2}},
|
||||
{.MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}},
|
||||
// .MOVDIR64B
|
||||
{.MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=1, explicit_count=2}},
|
||||
// .ENQCMD
|
||||
{.ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=3, explicit_count=2}},
|
||||
// .ENQCMDS
|
||||
{.ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=2, explicit_count=2}},
|
||||
// .AADD
|
||||
{.AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, explicit_count=2}},
|
||||
{.AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}},
|
||||
// .AAND
|
||||
{.AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=1, explicit_count=2}},
|
||||
{.AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=1, force_rex_w=true, explicit_count=2}},
|
||||
// .AOR
|
||||
{.AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=3, explicit_count=2}},
|
||||
{.AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=3, force_rex_w=true, explicit_count=2}},
|
||||
// .AXOR
|
||||
{.AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=2, explicit_count=2}},
|
||||
{.AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=2, force_rex_w=true, explicit_count=2}},
|
||||
// .XEND
|
||||
{.XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 213, {esc=._0F}},
|
||||
// .XTEST
|
||||
{.XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 214, {esc=._0F}},
|
||||
// .VMRUN
|
||||
{.VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 216, {esc=._0F}},
|
||||
// .VMMCALL
|
||||
{.VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 217, {esc=._0F}},
|
||||
// .VMLOAD
|
||||
{.VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 218, {esc=._0F}},
|
||||
// .VMSAVE
|
||||
{.VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 219, {esc=._0F}},
|
||||
// .STGI
|
||||
{.STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 220, {esc=._0F}},
|
||||
// .CLGI
|
||||
{.CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 221, {esc=._0F}},
|
||||
// .SKINIT
|
||||
{.SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 222, {esc=._0F}},
|
||||
// .INVLPGA
|
||||
{.INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 223, {esc=._0F}},
|
||||
// .INVLPGB
|
||||
{.INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 254, {esc=._0F}},
|
||||
// .TLBSYNC
|
||||
{.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 255, {esc=._0F}},
|
||||
// .PVALIDATE
|
||||
{.PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 255, {esc=._0F, prefix=3}},
|
||||
// .RMPADJUST
|
||||
{.RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 254, {esc=._0F, prefix=2}},
|
||||
// .RMPUPDATE
|
||||
{.RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 254, {esc=._0F, prefix=3}},
|
||||
// .PSMASH
|
||||
{.PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 255, {esc=._0F, prefix=2}},
|
||||
// .CLZERO
|
||||
{.CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 252, {esc=._0F}},
|
||||
// .MONITORX
|
||||
{.MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 250, {esc=._0F}},
|
||||
// .MWAITX
|
||||
{.MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 251, {esc=._0F}},
|
||||
// .RDPRU
|
||||
{.RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 253, {esc=._0F}},
|
||||
// .MCOMMIT
|
||||
{.MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 250, {esc=._0F, prefix=2}},
|
||||
}
|
||||
|
||||
@(rodata)
|
||||
CLOBBER_FORMS := [2395]lib.Clobber{
|
||||
CLOBBER_FORMS := [2451]lib.Clobber{
|
||||
// .MOV
|
||||
{written={0}, read={1}, writes_mem=true, reads_mem=true},
|
||||
{written={0}, read={1}, writes_mem=true, reads_mem=true},
|
||||
@@ -7185,6 +7287,108 @@ CLOBBER_FORMS := [2395]lib.Clobber{
|
||||
{written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}},
|
||||
{written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}},
|
||||
{written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}},
|
||||
// .SWAPGS
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .MONITOR
|
||||
{implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true},
|
||||
// .MWAIT
|
||||
{implicit_rd={.RAX, .RCX}, side_effects={.HALT}},
|
||||
// .CLAC
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .STAC
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .RDFSBASE
|
||||
{written={0}},
|
||||
{written={0}},
|
||||
// .RDGSBASE
|
||||
{written={0}},
|
||||
{written={0}},
|
||||
// .WRFSBASE
|
||||
{read={0}},
|
||||
{read={0}},
|
||||
// .WRGSBASE
|
||||
{read={0}},
|
||||
{read={0}},
|
||||
// .PTWRITE
|
||||
{read={0}, reads_mem=true},
|
||||
{read={0}, reads_mem=true},
|
||||
// .RDPID
|
||||
{written={0}},
|
||||
// .WBNOINVD
|
||||
{side_effects={.SERIALIZING, .PRIVILEGED}},
|
||||
// .SERIALIZE
|
||||
{side_effects={.SERIALIZING}},
|
||||
// .PREFETCH
|
||||
{read={0}, reads_mem=true, side_effects={.HINT}},
|
||||
// .TPAUSE
|
||||
{read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}},
|
||||
// .UMONITOR
|
||||
{read={0}, reads_mem=true},
|
||||
// .UMWAIT
|
||||
{read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}},
|
||||
// .MOVDIRI
|
||||
{read={0, 1}, writes_mem=true},
|
||||
{read={0, 1}, writes_mem=true},
|
||||
// .MOVDIR64B
|
||||
{read={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true},
|
||||
// .ENQCMD
|
||||
{read={0}, flags_wr={.ZF}, writes_mem=true, reads_mem=true},
|
||||
// .ENQCMDS
|
||||
{read={0}, flags_wr={.ZF}, writes_mem=true, reads_mem=true},
|
||||
// .AADD
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
// .AAND
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
// .AOR
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
// .AXOR
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
{read={0, 1}, writes_mem=true, reads_mem=true},
|
||||
// .XEND
|
||||
{side_effects={.CONTROL}},
|
||||
// .XTEST
|
||||
{flags_wr={.ZF}},
|
||||
// .VMRUN
|
||||
{implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}},
|
||||
// .VMMCALL
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .VMLOAD
|
||||
{implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}},
|
||||
// .VMSAVE
|
||||
{implicit_rd={.RAX}, writes_mem=true, side_effects={.PRIVILEGED}},
|
||||
// .STGI
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .CLGI
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .SKINIT
|
||||
{implicit_rd={.RAX}, side_effects={.PRIVILEGED}},
|
||||
// .INVLPGA
|
||||
{implicit_rd={.RAX, .RCX}, side_effects={.PRIVILEGED}},
|
||||
// .INVLPGB
|
||||
{implicit_rd={.RAX, .RCX, .RDX}, side_effects={.PRIVILEGED}},
|
||||
// .TLBSYNC
|
||||
{side_effects={.PRIVILEGED}},
|
||||
// .PVALIDATE
|
||||
{implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true},
|
||||
// .RMPADJUST
|
||||
{implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}},
|
||||
// .RMPUPDATE
|
||||
{implicit_wr={.RAX}, implicit_rd={.RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}},
|
||||
// .PSMASH
|
||||
{implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, side_effects={.PRIVILEGED}},
|
||||
// .CLZERO
|
||||
{implicit_rd={.RAX}, writes_mem=true, side_effects={.CACHE}},
|
||||
// .MONITORX
|
||||
{implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true},
|
||||
// .MWAITX
|
||||
{implicit_rd={.RAX, .RBX, .RCX}, side_effects={.HALT}},
|
||||
// .RDPRU
|
||||
{implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}},
|
||||
// .MCOMMIT
|
||||
{flags_wr={.CF}, side_effects={.FENCE}},
|
||||
}
|
||||
|
||||
@(rodata)
|
||||
@@ -8381,10 +8585,56 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
|
||||
.MOVBE = { 2383, 6},
|
||||
.RDRAND = { 2389, 3},
|
||||
.RDSEED = { 2392, 3},
|
||||
.SWAPGS = { 2395, 1},
|
||||
.MONITOR = { 2396, 1},
|
||||
.MWAIT = { 2397, 1},
|
||||
.CLAC = { 2398, 1},
|
||||
.STAC = { 2399, 1},
|
||||
.RDFSBASE = { 2400, 2},
|
||||
.RDGSBASE = { 2402, 2},
|
||||
.WRFSBASE = { 2404, 2},
|
||||
.WRGSBASE = { 2406, 2},
|
||||
.PTWRITE = { 2408, 2},
|
||||
.RDPID = { 2410, 1},
|
||||
.WBNOINVD = { 2411, 1},
|
||||
.SERIALIZE = { 2412, 1},
|
||||
.PREFETCH = { 2413, 1},
|
||||
.TPAUSE = { 2414, 1},
|
||||
.UMONITOR = { 2415, 1},
|
||||
.UMWAIT = { 2416, 1},
|
||||
.MOVDIRI = { 2417, 2},
|
||||
.MOVDIR64B = { 2419, 1},
|
||||
.ENQCMD = { 2420, 1},
|
||||
.ENQCMDS = { 2421, 1},
|
||||
.AADD = { 2422, 2},
|
||||
.AAND = { 2424, 2},
|
||||
.AOR = { 2426, 2},
|
||||
.AXOR = { 2428, 2},
|
||||
.XEND = { 2430, 1},
|
||||
.XTEST = { 2431, 1},
|
||||
.VMRUN = { 2432, 1},
|
||||
.VMMCALL = { 2433, 1},
|
||||
.VMLOAD = { 2434, 1},
|
||||
.VMSAVE = { 2435, 1},
|
||||
.STGI = { 2436, 1},
|
||||
.CLGI = { 2437, 1},
|
||||
.SKINIT = { 2438, 1},
|
||||
.INVLPGA = { 2439, 1},
|
||||
.INVLPGB = { 2440, 1},
|
||||
.TLBSYNC = { 2441, 1},
|
||||
.PVALIDATE = { 2442, 1},
|
||||
.RMPADJUST = { 2443, 1},
|
||||
.RMPUPDATE = { 2444, 1},
|
||||
.PSMASH = { 2445, 1},
|
||||
.CLZERO = { 2446, 1},
|
||||
.MONITORX = { 2447, 1},
|
||||
.MWAITX = { 2448, 1},
|
||||
.RDPRU = { 2449, 1},
|
||||
.MCOMMIT = { 2450, 1},
|
||||
}
|
||||
|
||||
// Emit descriptor per form (derived from ENCODE_FORMS via lib.form_to_recipe).
|
||||
ENCODE_RECIPES: [2395]lib.Form_Recipe
|
||||
ENCODE_RECIPES: [2451]lib.Form_Recipe
|
||||
@(init) _fill_recipes :: proc "contextless" () {
|
||||
for i in 0 ..< len(ENCODE_FORMS) {
|
||||
ENCODE_RECIPES[i] = lib.form_to_recipe(&ENCODE_FORMS[i])
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
+48
-11
@@ -85,7 +85,10 @@ struct Asm_amd64 {
|
||||
M_VMWRITE, M_VMFUNC, M_INVEPT, M_INVVPID, M_ENCLS, M_ENCLU, M_ENCLV, M_RDPKRU, M_WRPKRU, M_INCSSPD, M_INCSSPQ, M_RDSSPD, M_RDSSPQ, M_SAVEPREVSSP, M_RSTORSSP, M_WRSSD,
|
||||
M_WRSSQ, M_WRUSSD, M_WRUSSQ, M_SETSSBSY, M_CLRSSBSY, M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, M_XSAVEC64, M_XSAVES,
|
||||
M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, M_CMPXCHG16B, M_XADD,
|
||||
M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED,
|
||||
M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, M_SWAPGS, M_MONITOR, M_MWAIT, M_CLAC, M_STAC, M_RDFSBASE, M_RDGSBASE, M_WRFSBASE,
|
||||
M_WRGSBASE, M_PTWRITE, M_RDPID, M_WBNOINVD, M_SERIALIZE, M_PREFETCH, M_TPAUSE, M_UMONITOR, M_UMWAIT, M_MOVDIRI, M_MOVDIR64B, M_ENQCMD, M_ENQCMDS, M_AADD, M_AAND, M_AOR,
|
||||
M_AXOR, M_XEND, M_XTEST, M_VMRUN, M_VMMCALL, M_VMLOAD, M_VMSAVE, M_STGI, M_CLGI, M_SKINIT, M_INVLPGA, M_INVLPGB, M_TLBSYNC, M_PVALIDATE, M_RMPADJUST, M_RMPUPDATE,
|
||||
M_PSMASH, M_CLZERO, M_MONITORX, M_MWAITX, M_RDPRU, M_MCOMMIT,
|
||||
|
||||
MNEMONIC_COUNT
|
||||
};
|
||||
@@ -407,9 +410,9 @@ struct Asm_amd64 {
|
||||
};
|
||||
|
||||
|
||||
static EncodeRun const raw_encode_runs [1192];
|
||||
static u8 const raw_encode_forms [38320];
|
||||
static u8 const raw_clobber_forms[38320];
|
||||
static EncodeRun const raw_encode_runs [1238];
|
||||
static u8 const raw_encode_forms [39216];
|
||||
static u8 const raw_clobber_forms[39216];
|
||||
|
||||
StringMap<Mnemonic> mnemonic_map;
|
||||
StringMap<Prefix> prefix_map;
|
||||
@@ -733,7 +736,10 @@ String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] {
|
||||
str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), str_lit("rstorssp"), str_lit("wrssd"),
|
||||
str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), str_lit("xsavec64"), str_lit("xsaves"),
|
||||
str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), str_lit("xadd"),
|
||||
str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"),
|
||||
str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), str_lit("swapgs"), str_lit("monitor"), str_lit("mwait"), str_lit("clac"), str_lit("stac"), str_lit("rdfsbase"), str_lit("rdgsbase"), str_lit("wrfsbase"),
|
||||
str_lit("wrgsbase"), str_lit("ptwrite"), str_lit("rdpid"), str_lit("wbnoinvd"), str_lit("serialize"), str_lit("prefetch"), str_lit("tpause"), str_lit("umonitor"), str_lit("umwait"), str_lit("movdiri"), str_lit("movdir64b"), str_lit("enqcmd"), str_lit("enqcmds"), str_lit("aadd"), str_lit("aand"), str_lit("aor"),
|
||||
str_lit("axor"), str_lit("xend"), str_lit("xtest"), str_lit("vmrun"), str_lit("vmmcall"), str_lit("vmload"), str_lit("vmsave"), str_lit("stgi"), str_lit("clgi"), str_lit("skinit"), str_lit("invlpga"), str_lit("invlpgb"), str_lit("tlbsync"), str_lit("pvalidate"), str_lit("rmpadjust"), str_lit("rmpupdate"),
|
||||
str_lit("psmash"), str_lit("clzero"), str_lit("monitorx"), str_lit("mwaitx"), str_lit("rdpru"), str_lit("mcommit"),
|
||||
};
|
||||
String const Asm_amd64::prefix_strings[Asm_amd64::PREFIX_COUNT] {
|
||||
str_lit(""), str_lit("es"), str_lit("cs"), str_lit("ss"), str_lit("ds"), str_lit("rex"), str_lit("evex"), str_lit("fs"), str_lit("gs"), str_lit("vex"), str_lit("lock"), str_lit("repne"), str_lit("rep"),
|
||||
@@ -770,7 +776,7 @@ String const Asm_amd64::register_strings[Asm_amd64::REG_COUNT] {
|
||||
str_lit("bnd2"), str_lit("bnd3"), str_lit("mm0"), str_lit("mm1"), str_lit("mm2"), str_lit("mm3"), str_lit("mm4"), str_lit("mm5"), str_lit("mm6"), str_lit("mm7"), str_lit("st0"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("st5"),
|
||||
str_lit("st6"), str_lit("st7"), str_lit("rip"),
|
||||
};
|
||||
Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1192] = {
|
||||
Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1238] = {
|
||||
{ 0, 0}, { 0, 32}, { 32, 9}, { 41, 5}, { 46, 5}, { 51, 1}, { 52, 7}, { 59, 9}, { 68, 6}, { 74, 3}, { 77, 19}, { 96, 19}, { 115, 19}, { 134, 19}, { 153, 4}, { 157, 13},
|
||||
{ 170, 4}, { 174, 4}, { 178, 6}, { 184, 6}, { 190, 4}, { 194, 19}, { 213, 19}, { 232, 19}, { 251, 19}, { 270, 4}, { 274, 12}, { 286, 12}, { 298, 12}, { 310, 12}, { 322, 12}, { 334, 12},
|
||||
{ 346, 12}, { 358, 12}, { 370, 6}, { 376, 6}, { 382, 6}, { 388, 6}, { 394, 6}, { 400, 6}, { 406, 3}, { 409, 3}, { 412, 3}, { 415, 3}, { 418, 3}, { 421, 6}, { 427, 2}, { 429, 2},
|
||||
@@ -845,9 +851,12 @@ Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1192] = {
|
||||
{2322, 1}, {2323, 1}, {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, {2335, 1}, {2336, 1}, {2337, 1},
|
||||
{2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, {2351, 1}, {2352, 1}, {2353, 1},
|
||||
{2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 2}, {2367, 4}, {2371, 1}, {2372, 1}, {2373, 4},
|
||||
{2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3},
|
||||
{2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3}, {2395, 1}, {2396, 1}, {2397, 1}, {2398, 1}, {2399, 1}, {2400, 2}, {2402, 2}, {2404, 2},
|
||||
{2406, 2}, {2408, 2}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 1}, {2416, 1}, {2417, 2}, {2419, 1}, {2420, 1}, {2421, 1}, {2422, 2}, {2424, 2}, {2426, 2},
|
||||
{2428, 2}, {2430, 1}, {2431, 1}, {2432, 1}, {2433, 1}, {2434, 1}, {2435, 1}, {2436, 1}, {2437, 1}, {2438, 1}, {2439, 1}, {2440, 1}, {2441, 1}, {2442, 1}, {2443, 1}, {2444, 1},
|
||||
{2445, 1}, {2446, 1}, {2447, 1}, {2448, 1}, {2449, 1}, {2450, 1},
|
||||
};
|
||||
u8 const Asm_amd64::raw_encode_forms[38320] = {
|
||||
u8 const Asm_amd64::raw_encode_forms[39216] = {
|
||||
0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x06, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x07, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x08, 0x08, 0x00,
|
||||
0x01, 0x00, 0x01, 0x05, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x08, 0x08, 0x00,
|
||||
0x01, 0x00, 0x01, 0x12, 0x00, 0x00, 0x04, 0x05, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x13, 0x00, 0x00, 0x04, 0x06, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x14, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x15, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x08, 0x08, 0x00,
|
||||
@@ -1446,9 +1455,23 @@ u8 const Asm_amd64::raw_encode_forms[38320] = {
|
||||
0xa2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa5, 0x04, 0x02, 0x0b, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x08, 0x00,
|
||||
0xa5, 0x04, 0x03, 0x0c, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x08, 0x00, 0xa5, 0x04, 0x04, 0x0d, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf0, 0x00, 0x02, 0x08, 0x08, 0x00, 0xa5, 0x04, 0x0b, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x00, 0x08, 0x00, 0xa5, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x00, 0x08, 0x00,
|
||||
0xa5, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x08, 0x08, 0x00, 0xa6, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa6, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa6, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x08, 0x05, 0x00,
|
||||
0xa7, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00,
|
||||
0xa7, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, 0xa8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf8, 0x01, 0x00, 0x00, 0x00,
|
||||
0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc8, 0x01, 0x00, 0x00, 0x00, 0xaa, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc9, 0x01, 0x00, 0x00, 0x00, 0xab, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xca, 0x01, 0x00, 0x00, 0x00, 0xac, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xcb, 0x01, 0x00, 0x00, 0x00,
|
||||
0xad, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x00, 0x09, 0x00, 0x05, 0x00, 0xad, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x00, 0x09, 0x08, 0x05, 0x00, 0xae, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x01, 0x09, 0x00, 0x05, 0x00, 0xae, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x01, 0x09, 0x08, 0x05, 0x00,
|
||||
0xaf, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x02, 0x09, 0x00, 0x05, 0x00, 0xaf, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x02, 0x09, 0x08, 0x05, 0x00, 0xb0, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x03, 0x09, 0x00, 0x05, 0x00, 0xb0, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x03, 0x09, 0x08, 0x05, 0x00,
|
||||
0xb1, 0x04, 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x04, 0x09, 0x00, 0x05, 0x00, 0xb1, 0x04, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x04, 0x09, 0x08, 0x05, 0x00, 0xb2, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x09, 0x00, 0x05, 0x00, 0xb3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00,
|
||||
0xb4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe8, 0x01, 0x00, 0x00, 0x00, 0xb5, 0x04, 0x0a, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x01, 0x00, 0x05, 0x00, 0xb6, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x06, 0x05, 0x00, 0x05, 0x00, 0xb7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x06, 0x09, 0x00, 0x05, 0x00,
|
||||
0xb8, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x06, 0x0d, 0x00, 0x05, 0x00, 0xb9, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x08, 0x00, 0xb9, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x08, 0x08, 0x00, 0xba, 0x04, 0x04, 0x11, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x06, 0x00, 0x08, 0x00,
|
||||
0xbb, 0x04, 0x04, 0x11, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x0e, 0x00, 0x08, 0x00, 0xbc, 0x04, 0x04, 0x11, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x0a, 0x00, 0x08, 0x00, 0xbd, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x02, 0x00, 0x08, 0x00, 0xbd, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x02, 0x08, 0x08, 0x00,
|
||||
0xbe, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x06, 0x00, 0x08, 0x00, 0xbe, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x06, 0x08, 0x08, 0x00, 0xbf, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0e, 0x00, 0x08, 0x00, 0xbf, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0e, 0x08, 0x08, 0x00,
|
||||
0xc0, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0a, 0x00, 0x08, 0x00, 0xc0, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0a, 0x08, 0x08, 0x00, 0xc1, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd5, 0x01, 0x00, 0x00, 0x00, 0xc2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd6, 0x01, 0x00, 0x00, 0x00,
|
||||
0xc3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd8, 0x01, 0x00, 0x00, 0x00, 0xc4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd9, 0x01, 0x00, 0x00, 0x00, 0xc5, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xda, 0x01, 0x00, 0x00, 0x00, 0xc6, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdb, 0x01, 0x00, 0x00, 0x00,
|
||||
0xc7, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdc, 0x01, 0x00, 0x00, 0x00, 0xc8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdd, 0x01, 0x00, 0x00, 0x00, 0xc9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xde, 0x01, 0x00, 0x00, 0x00, 0xca, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf, 0x01, 0x00, 0x00, 0x00,
|
||||
0xcb, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x01, 0x00, 0x00, 0x00, 0xcc, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x01, 0x00, 0x00, 0x00, 0xcd, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x0d, 0x00, 0x00, 0x00, 0xce, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x09, 0x00, 0x00, 0x00,
|
||||
0xcf, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x0d, 0x00, 0x00, 0x00, 0xd0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x09, 0x00, 0x00, 0x00, 0xd1, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfc, 0x01, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x01, 0x00, 0x00, 0x00,
|
||||
0xd3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfb, 0x01, 0x00, 0x00, 0x00, 0xd4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfd, 0x01, 0x00, 0x00, 0x00, 0xd5, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x09, 0x00, 0x00, 0x00,
|
||||
};
|
||||
u8 const Asm_amd64::raw_clobber_forms[38320] = {
|
||||
u8 const Asm_amd64::raw_clobber_forms[39216] = {
|
||||
0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
@@ -2047,5 +2070,19 @@ u8 const Asm_amd64::raw_clobber_forms[38320] = {
|
||||
0x00, 0x00, 0xc0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
|
||||
0x00, 0x01, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00,
|
||||
0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x0d, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x0d, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00,
|
||||
0x00, 0x00, 0x01, 0x00, 0x05, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x09, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
|
||||
};
|
||||
Reference in new issue
Block a user