8 Commits

Include renames

Author	SHA1	Message	Date
gingerBill	648c418fc4	Restrict riscv to only allow [base + disp] (i.e. disallow index*scale style things)	2026-08-21 14:31:58 +01:00
gingerBill	4a4a5045f8	Check for float register width exactly for risc-v frontend	2026-08-21 12:19:02 +01:00
gingerBill	a604ddceb1	Support pseudo macro mnemonics (for RISC-V) in the frontend	2026-08-21 11:47:41 +01:00
gingerBill	d0fb380c20	Support riscv _aq _rl _aqrl suffixes for mnemonics	2026-08-21 01:05:47 +01:00
gingerBill	de8c0dc4fe	Fix register width test for risc-v, and improve operand slot type inference for risc-v	2026-08-21 00:38:34 +01:00
gingerBill	09204e8982	Correct risc-v aliases	2026-08-20 19:48:30 +01:00
gingerBill	7a7bfea0bd	Begin work on pseudo mnemonics in the checker	2026-08-20 19:12:44 +01:00
gingerBill	43ff42bf33	Add asm_tables_riscv.cpp	2026-08-20 14:44:10 +01:00