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Brendan PunskyandClaude Opus 5.5
ec7256a481
MVE's rows were, in the table's own words, educated estimates pending
LLVM verification: one element size per mnemonic, contiguous loads given
a 12-bit offset, the accumulating and plain reductions sharing a word,
VPT's mask in the wrong bits. On the M-profile target 2114 random words
decoded to nothing, 410 to the wrong instruction, and the Cortex-M55
object failed on 300 words.
tablegen/mve_table.odin replaces them: a flat list, every row of it read
off llvm-mc. Each instruction is assembled, each operand varied over its
range to find the bits it occupies -- which must be the bits of the
encoding the row names -- and every other bit fixed. Where one word has
several spellings (vmladav is vmlav, vldrb.s8 is vldrb.u8, vmla.s16 is
vmla.i16) the one llvm prints decodes and the others are encode-only.
VPT is VCMP opening a block, so its rows are VCMP's with the mask freed.
What MVE needed that nothing had:
* Addresses: [Rn, #imm7] scaled by the element, by the memory element
for the widening loads, a vector of bases [Qm, #imm], a vector of
offsets [Rn, Qm, uxtw #s], and the interleaving loads' [Rn]!.
* VPT and VPST masks, spelled on the mnemonic as IT's are, and the
T or E an instruction inside the block takes, which the decoder now
follows and the printer writes -- `vaddt.i32`. Without it a listing
with a VPT block does not reassemble.
* VCMP's three condition bits, lanes and lane pairs of Q registers,
MVE's shift amounts, which lack Advanced SIMD's L bit, VCMUL's
rotation, and the scalar long shifts' register pair -- which may not
be SP, and where the decoder now falls back to ORRS.
* The mnemonics llvm has and the table did not: VMULH, VADC, VMAXA,
VMOVLB, ASRL, SQRSHRL and the rest of the scalar shifts. VMLALB and
its kin, which do not exist, are gone.
Also on v8.1-M: VLDR and VSTR of the floating-point system registers,
BFCSEL's else target and condition, which it printed as a number,
LDC2L and STC2L on coprocessors 10 and 11 where llvm takes them.
The harness has a VPT-block suite, and the corpus mode takes VPT blocks
as units the way it takes IT blocks. tests/pipeline.odin has an MVE
golden listing, assembled by llvm-mc, that round-trips byte for byte.
Every suite now passes outright -- A32, T16, T32, IT and VPT -- with no
word decoded wrong, extra, missing or unassemblable, and every decoded
word re-encodes; so do the Cortex-M0, M7, M33 and M55 and the A15 and
A53 objects.
The last #partial switch statements in the package are exhaustive now,
and the sweep's fill values are a table.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01BbUtG4UwNiMydtMW2qGhw4