Jeroen van Rijn 5923d147e5 Add hardware-accelerated CRC32 and core:hash ...

- amd64: PCLMULQDQ folding for inputs of 16 bytes and up, and a 256-bit
  VPCLMULQDQ path from 256 bytes. The features are detected with
  CPUID/XGETBV at startup, or assumed when `-microarch` provides them.
- arm64: CRC32 instructions for inputs under 192 bytes and all tails,
  PMULL folding above that. Used on Darwin, and elsewhere when
  -microarch enables crc and aes.
- Generic fallback: slice-by-16 replaces slice-by-8, 1.3x faster.
- New crc32_combine(crc1, crc2, length2) for joining CRCs of adjacent
  pieces (parallel hashing).
- core:simd/x86: add `_mm256_clmulepi64_epi128`.
- Tests: every length 0-1100 at 16 alignments against a bitwise
  reference, seed chaining, and `crc32_combine`.

Throughput in GB/s, old -> new:

	size     5950X          M4
	32       1.46 ->  3.29  1.47 ->  8.20
	256      2.35 -> 16.1   2.40 -> 16.6
	1 KiB    2.51 -> 33.0   2.54 -> 29.9
	64 KiB   2.57 -> 38.1   2.62 -> 37.9

2026-11-01 22:11:43 +01:00

..

arm

Impl simd arm neon intrinsics set

2026-10-10 11:48:02 +03:00

x86

Add hardware-accelerated CRC32 and core:hash

2026-11-01 22:11:43 +01:00

simd.odin

Impl simd x86 sse rest cleanup

2026-10-29 16:53:06 +03:00