mirror of
https://github.com/odin-lang/Odin.git
synced 2026-10-08 22:01:47 -04:00
gingerBill
654b3a8895
Parse `[...]` as `term { (+|-) term }` where each term is `operand [ (*|<<|>>) operand ]`.
This allows for constant-only terms to be folded in-place, especially for things like displacement.
e.g. `[p + 8*32]` means `[p + 256]`.
Term order is also free: `[8 + p]` == `[p + 8]`
1058 lines
31 KiB
C++
1058 lines
31 KiB
C++
// check_asm_cfg.cpp
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enum {
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ASM_WIDTH_REG_COUNT = 16
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};
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// Sub-register width tracking
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// 0 means "this instruction does not read/write that named register"
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struct AsmRegW {
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u8 e[ASM_WIDTH_REG_COUNT];
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};
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gb_internal u8 asm_reg_def_width_after(u8 prev, u8 w) {
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bool x86 = build_context.metrics.arch == TargetArch_amd64 ||
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build_context.metrics.arch == TargetArch_i386; // TODO(bill): actually support x86 32-bit :P
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if (x86 && w == 32) {
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return 64;
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}
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return gb_max(prev, w);
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}
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gb_internal i32 asm_reg_index_from_bit(u16 bit) {
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for (i32 i = 0; i < ASM_WIDTH_REG_COUNT; i++) {
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if (bit == cast(u16)(1u << i)) {
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return i;
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}
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}
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return -1;
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}
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struct AsmBlock {
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i32 first; // instruction index
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i32 last;
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Array<i32> succs;
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u16 in_defs;
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u16 out_defs;
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u16 in_flags;
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u16 out_flags;
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u16 live_in_regs;
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u16 live_out_regs;
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PtrSet<Entity *> in_params;
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PtrSet<Entity *> out_params;
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bool reachable;
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};
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struct AsmInstructionFacts {
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AstAsmInstruction *node;
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String name;
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u16 gen_flags; // flag bits this instruction defines
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u16 read_flags;
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u16 gen_regs;
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u16 read_regs;
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// Sub-register widths, indexed by reg bit-index.
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AsmRegW read_reg_w;
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AsmRegW gen_reg_w;
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Array<Entity *> gen_params;
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Array<Entity *> read_params;
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bool is_control;
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bool is_conditional;
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bool is_terminal;
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Entity *branch_target;
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i32 block_id;
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};
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gb_internal u16 asm_full_kill_mask(AsmInstructionFacts *f) {
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u16 full = cast(u16)(build_context.metrics.ptr_size*8);
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u16 kill = 0;
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for (u16 bit = 1; bit != 0; bit <<= 1) {
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if ((f->gen_regs & bit) == 0) {
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continue;
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}
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i32 idx = asm_reg_index_from_bit(bit);
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u8 w = 0;
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if (idx >= 0) {
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w = f->gen_reg_w.e[idx];
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}
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if (w == 0 || asm_reg_def_width_after(0, w) >= full) {
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kill |= bit;
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}
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}
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return kill;
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}
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struct AsmCfg {
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// Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints).
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u16 implicit_clobbered_regs;
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u16 explicitly_produced_regs;
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u16 stale_outputs;
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bool saw_any_instructions; // NOTE(bill): An empty diverging body cannot diverge.
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// NOTE(bill): Related to #align_stack
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// any call/branch (CONTROL) or memory effect that could require the stack
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// to be realigned. If none occurred, #align_stack is redundant.
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bool saw_call_or_mem;
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// Purity test
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bool can_be_pure;
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char const *impure_reason;
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Ast * impure_reason_node;
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Array<AstAsmInstruction *> insts; // program-order (only for fact-carrying instrs)
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Array<AsmBlock> blocks;
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PtrMap<Entity *, i32> entity_to_index;
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Array<u16> decl_pin_bit;
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u64 universe_pm;
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};
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gb_internal void asm_cfg_init(AsmCfg *cfg) {
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map_init(&cfg->entity_to_index);
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cfg->decl_pin_bit.allocator = heap_allocator();
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cfg->can_be_pure = true;
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};
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gb_internal void asm_cfg_destroy(AsmCfg *cfg) {
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for (auto &block : cfg->blocks) {
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array_free(&block.succs);
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ptr_set_destroy(&block.in_params);
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ptr_set_destroy(&block.out_params);
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}
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array_free(&cfg->blocks);
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array_free(&cfg->insts);
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map_destroy(&cfg->entity_to_index);
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array_free(&cfg->decl_pin_bit);
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}
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gb_internal i32 asm_cfg_label_block_index(Entity *entity) {
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if (entity != nullptr && entity->kind == Entity_Label) {
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return entity->Label.asm_block_index;
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}
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return -1;
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}
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gb_internal bool asm_cfg_label_block_index_set(Entity *entity, i32 index) {
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if (entity != nullptr && entity->kind == Entity_Label) {
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GB_ASSERT(entity->Label.asm_block_index < 0);
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entity->Label.asm_block_index = index;
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}
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return false;
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}
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// The physical-register bit a decl is pinned to. A width-view carries no pin of
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// its own; it inherits its source decl's pin. Returns 0 for unpinned decls.
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template <typename AsmCtx>
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gb_internal u16 asm_decl_resolve_pin_bit(AsmCtx *asm_ctx, Array<AsmTemplateEntityDecl> const &decls, i32 di) {
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if (di < 0 || di >= cast(i32)decls.count) {
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return 0;
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}
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auto const &ed = decls[di];
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if (ed.pin.len != 0) {
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return asm_ctx->clobber_bit_for_reg_name(ed.pin);
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}
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if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) {
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String src_pin = decls[ed.view_of].pin;
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if (src_pin.len != 0) {
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return asm_ctx->clobber_bit_for_reg_name(src_pin);
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}
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}
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return 0;
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}
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template <typename AsmCtx>
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gb_internal u16 asm_decl_resolve_flag_bit(AsmCtx *asm_ctx, AsmTemplateEntityDecl const &ed) {
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if (ed.pin_flag.len == 0) {
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return 0;
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}
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auto flags = asm_ctx->flag_from_name(ed.pin_flag);
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return cast(u16)flags;
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}
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template <typename AsmCtx>
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gb_internal void asm_cfg_populate_decls(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *entity) {
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auto const &decls = entity->AsmTemplate.decls;
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cfg->universe_pm = 0;
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if (decls.count > 64) {
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// NOTE(bill): check_asm_cfg_analyse will err on this since this is exceed the maximum number of declarations
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return;
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}
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array_resize(&cfg->decl_pin_bit, decls.count);
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for_array(i, decls) {
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Entity *e = decls[i].entity;
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cfg->decl_pin_bit[i] = asm_decl_resolve_pin_bit(asm_ctx, decls, cast(i32)i);
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if (e != nullptr) {
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if (decls[i].view_of >= 0) {
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// NOTE(bill): A view shares its source's lattice bit, as it is not an independent value.
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i32 src_i = decls[i].view_of;
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Entity *src_e = decls[src_i].entity;
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if (src_e != nullptr) {
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map_set(&cfg->entity_to_index, e, src_i);
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}
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// NOTE(bill): No need to set a universe bit for the view as the source already has one
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} else {
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map_set(&cfg->entity_to_index, e, cast(i32)i);
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cfg->universe_pm |= (cast(u64)1 << i);
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}
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}
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}
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}
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template <typename AsmCtx>
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gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, Entity *entity) {
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ast_node(at, AsmTemplate, at_node);
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asm_cfg_populate_decls(asm_ctx, cfg, entity);
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cfg->insts.allocator = heap_allocator();
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cfg->blocks.allocator = heap_allocator();
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bool need_leader = true;
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// Build basic blocks over the template body. A leader is: the first instruction, any
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// instruction preceded by a label, and any instruction following a control transfer.
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for (Ast *node : at->instructions) {
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if (node->kind == Ast_AsmLabelDecl) {
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// Every label between two instructions names the block the *next* instruction
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// opens; consecutive labels share it. A trailing label maps to blocks.count.
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Entity *le = node->AsmLabelDecl.name->Ident.entity;
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if (le != nullptr) {
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asm_cfg_label_block_index_set(le, cast(i32)cfg->blocks.count);
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}
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need_leader = true;
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continue;
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}
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if (node->kind != Ast_AsmInstruction) {
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continue; // directives are straight-line filler; no CFG effect
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}
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AstAsmInstruction *instr = &node->AsmInstruction;
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AsmInstructionFacts *facts = instr->facts;
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// Prefixes and pseudo-macro ops (li/la) carry no facts and never branch.
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if (need_leader || cfg->blocks.count == 0) {
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AsmBlock b = {};
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b.first = cast(i32)cfg->insts.count;
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b.last = cast(i32)cfg->insts.count;
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b.succs.allocator = heap_allocator();
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array_add(&cfg->blocks, b);
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need_leader = false;
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}
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i32 bi = cast(i32)cfg->blocks.count - 1;
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i32 ii = cast(i32)cfg->insts.count;
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array_add(&cfg->insts, instr);
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cfg->blocks[bi].last = ii;
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if (facts != nullptr) {
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facts->block_id = bi;
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if (facts->is_control) {
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need_leader = true;
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}
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}
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}
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for_array(bi, cfg->blocks) { // Calculate the edges for the blocks
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AsmBlock *b = &cfg->blocks[bi];
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AstAsmInstruction *last = cfg->insts[b->last];
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AsmInstructionFacts *lf = last->facts;
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i32 branch_succ = -1;
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bool fallthrough = true;
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if (lf != nullptr && lf->is_control) {
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if (lf->branch_target != nullptr) {
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i32 t = asm_cfg_label_block_index(lf->branch_target);
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if (0 <= t && t < cast(i32)cfg->blocks.count) {
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branch_succ = t;
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}
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// For `t == blocks.count`, this implies a jump to the implicit end, and is handled as "leaves" below
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}
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// e.g. jmp/ret/hlt (and, conservatively, call) do not fall through in this model.
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if (lf->is_terminal) {
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fallthrough = false;
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}
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}
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if (branch_succ >= 0) {
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array_add(&b->succs, branch_succ);
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}
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if (fallthrough) {
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i32 next = cast(i32)bi + 1;
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if (next < cast(i32)cfg->blocks.count) {
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array_add(&b->succs, next);
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}
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}
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}
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if (cfg->blocks.count != 0) { // Reachability determination
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Array<i32> stack = {};
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stack.allocator = heap_allocator();
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defer (array_free(&stack));
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cfg->blocks[0].reachable = true;
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array_add(&stack, cast(i32)0);
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while (stack.count > 0) {
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i32 bi = stack[stack.count-1];
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stack.count -= 1;
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for (i32 s : cfg->blocks[bi].succs) {
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if (s >= 0 && s < cast(i32)cfg->blocks.count && !cfg->blocks[s].reachable) {
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cfg->blocks[s].reachable = true;
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array_add(&stack, s);
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}
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}
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}
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}
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}
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gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, i32 bi) {
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AsmBlock const *b = &cfg->blocks[bi];
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AstAsmInstruction *last = cfg->insts[b->last];
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AsmInstructionFacts *lf = last->facts;
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if (lf != nullptr && lf->branch_target != nullptr) {
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i32 t = asm_cfg_label_block_index(lf->branch_target);
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if (t >= 0 && t >= cast(i32)cfg->blocks.count) {
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return true; // 'jmp .end' — falls into the implicit return
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}
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}
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bool terminal = (lf != nullptr) && lf->is_terminal;
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if (!terminal && (bi+1 >= cast(i32)cfg->blocks.count)) {
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return true; // straight-line/conditional-tail with nothing after it
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}
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return false;
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}
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template <typename AsmCtx>
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gb_internal void check_asm_cfg_report_undef_reg(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *tmpl_entity,
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AstAsmInstruction *instr, String name, u16 bit) {
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char const *rname = asm_ctx->clobber_reg_bit_name(bit);
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String owner = {};
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char const *role = nullptr;
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auto const &decls = tmpl_entity->AsmTemplate.decls;
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for_array(i, decls) {
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auto const &ed = decls[i];
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if (ed.entity == nullptr || cfg->decl_pin_bit[i] != bit) {
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continue;
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}
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if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) {
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owner = ed.entity->token.string;
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role = "output";
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break;
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}
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if (ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0) {
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owner = ed.entity->token.string;
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role = "scratch";
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break;
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}
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}
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if (role != nullptr) {
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error(instr->name,
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"'%.*s' implicitly reads %%%s, which is bound to the %s parameter '%.*s', "
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"but nothing writes %%%s on all paths reaching here; write to it (e.g. into '%.*s') first",
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LIT(name), rname, role, LIT(owner), rname, LIT(owner));
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} else {
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error(instr->name,
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"'%.*s' implicitly reads %%%s, but nothing in this template produces a value for it "
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"on all paths reaching here; pin an input to %%%s, or write %%%s first",
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LIT(name), rname, rname, rname);
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}
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}
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template <typename AsmCtx>
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gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerContext *ctx, Entity *entity) {
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GB_ASSERT(entity->kind == Entity_AsmTemplate);
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auto *ate = &entity->AsmTemplate;
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auto const &decls = ate->decls;
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bool diverging = entity->type->Proc.diverging;
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if (cfg->blocks.count == 0) {
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// With an empty body, the CFG cannot really do nothing
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if (diverging && !cfg->saw_any_instructions) {
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error(entity->token, "This 'asm' template is declared as diverging (-> !) but its body is empty and cannot diverge");
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}
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return;
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}
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if (decls.count > 64) {
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error(entity->token, "'asm' templates cannot have more than 64 total parameter declarations, got %td", decls.count);
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return;
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}
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u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED;
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u16 const FLAG_TOP = cast(u16)~cast(u16)0;
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u64 const universe_pm = cfg->universe_pm;
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auto bit_of = [&](Entity *e) -> u64 {
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i32 *ix = map_get(&cfg->entity_to_index, e);
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return ix ? (cast(u64)1 << *ix) : cast(u64)0;
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};
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// NOTE(bill): entry seed intiailization which mirrors the linear seeding of defined_regs
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u16 seed_regs = 0;
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u64 seed_pm = 0;
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AsmRegW entry_seed_w = {};
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for_array(i, decls) {
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auto const &ed = decls[i];
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u16 pin_bit = cfg->decl_pin_bit[i];
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bool is_input_pin = false;
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if (ed.no_init) {
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seed_pm |= bit_of(ed.entity);
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seed_regs |= pin_bit;
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is_input_pin = true;
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}
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switch (ed.param_group) {
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case AsmTemplateEntityDeclParamGroup_Input:
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seed_pm |= bit_of(ed.entity);
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seed_regs |= pin_bit;
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is_input_pin = true;
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break;
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case AsmTemplateEntityDeclParamGroup_Output:
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if (ed.tie >= 0) {
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seed_pm |= bit_of(ed.entity);
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}
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break;
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}
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if (is_input_pin && pin_bit != 0 && ed.entity != nullptr) {
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i32 wi = asm_reg_index_from_bit(pin_bit);
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if (wi >= 0) {
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i32 tw = cast(i32)(type_size_of(ed.entity->type) * 8);
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if (tw > 255) tw = 255;
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entry_seed_w.e[wi] = gb_max(entry_seed_w.e[wi], cast(u8)tw);
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}
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}
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}
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// NOTE(bill): #preserve
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u16 preserve_bits = 0;
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for (String const ® : ate->preserve_registers_set) {
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preserve_bits |= asm_ctx->clobber_bit_for_reg_name(reg);
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}
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seed_regs |= preserve_bits;
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{
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u8 full = cast(u8)(build_context.metrics.ptr_size * 8);
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for (i32 idx = 0; idx < ASM_WIDTH_REG_COUNT; idx++) {
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if (preserve_bits & cast(u16)(1u << idx)) {
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entry_seed_w.e[idx] = gb_max(entry_seed_w.e[idx], full);
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}
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}
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}
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isize const n = cfg->blocks.count;
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auto in_regs = slice_make<u16>(heap_allocator(), n); defer (slice_free(&in_regs, heap_allocator()));
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auto out_regs = slice_make<u16>(heap_allocator(), n); defer (slice_free(&out_regs, heap_allocator()));
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auto gen_regs = slice_make<u16>(heap_allocator(), n); defer (slice_free(&gen_regs, heap_allocator()));
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auto in_flags = slice_make<u16>(heap_allocator(), n); defer (slice_free(&in_flags, heap_allocator()));
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auto out_flags = slice_make<u16>(heap_allocator(), n); defer (slice_free(&out_flags, heap_allocator()));
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auto gen_flags = slice_make<u16>(heap_allocator(), n); defer (slice_free(&gen_flags, heap_allocator()));
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|
auto in_pm = slice_make<u64>(heap_allocator(), n); defer (slice_free(&in_pm, heap_allocator()));
|
|
auto out_pm = slice_make<u64>(heap_allocator(), n); defer (slice_free(&out_pm, heap_allocator()));
|
|
auto gen_pm = slice_make<u64>(heap_allocator(), n); defer (slice_free(&gen_pm, heap_allocator()));
|
|
|
|
// Sub-register width lattice
|
|
auto in_w = slice_make<AsmRegW>(heap_allocator(), n); defer (slice_free(&in_w, heap_allocator()));
|
|
auto out_w = slice_make<AsmRegW>(heap_allocator(), n); defer (slice_free(&out_w, heap_allocator()));
|
|
auto gen_w = slice_make<AsmRegW>(heap_allocator(), n); defer (slice_free(&gen_w, heap_allocator()));
|
|
|
|
// predecessors, restricted to reachable blocks
|
|
auto preds = slice_make<Array<i32>>(heap_allocator(), n);
|
|
for_array(i, preds) {
|
|
preds[i].allocator = heap_allocator();
|
|
}
|
|
defer ({
|
|
for_array(i, preds) {
|
|
array_free(&preds[i]);
|
|
}
|
|
slice_free(&preds, heap_allocator());
|
|
});
|
|
for_array(bi, cfg->blocks) {
|
|
AsmBlock *block = &cfg->blocks[bi];
|
|
if (!block->reachable) {
|
|
continue;
|
|
}
|
|
for (i32 s : block->succs) {
|
|
if (0 <= s && s < cast(i32)n &&
|
|
cfg->blocks[s].reachable) {
|
|
array_add(&preds[s], cast(i32)bi);
|
|
}
|
|
}
|
|
}
|
|
|
|
for_array(bi, cfg->blocks) {
|
|
u16 gr = 0;
|
|
u16 gf = 0;
|
|
u64 gp = 0;
|
|
AsmRegW gw = {};
|
|
|
|
AsmBlock const &b = cfg->blocks[bi];
|
|
for (i32 ii = b.first; ii <= b.last; ii++) {
|
|
AsmInstructionFacts *f = cfg->insts[ii]->facts;
|
|
if (f == nullptr) {
|
|
continue;
|
|
}
|
|
gr |= f->gen_regs;
|
|
gf |= f->gen_flags;
|
|
for (Entity *pe : f->gen_params) {
|
|
gp |= bit_of(pe);
|
|
}
|
|
for (int w_idx = 0; w_idx < ASM_WIDTH_REG_COUNT; w_idx++) {
|
|
u8 w = f->gen_reg_w.e[w_idx];
|
|
if (w != 0) {
|
|
gw.e[w_idx] = asm_reg_def_width_after(gw.e[w_idx], w);
|
|
}
|
|
}
|
|
}
|
|
gen_regs [bi] = gr;
|
|
gen_flags[bi] = gf;
|
|
gen_pm [bi] = gp;
|
|
gen_w [bi] = gw;
|
|
}
|
|
|
|
// NOTE(bill): initialize the blocks
|
|
// entry is from the seeds and every other reachable block from TOP (intersection)
|
|
for_array(bi, cfg->blocks) {
|
|
if (!cfg->blocks[bi].reachable) {
|
|
continue;
|
|
}
|
|
if (bi == 0) {
|
|
in_regs [bi] = seed_regs;
|
|
in_pm [bi] = seed_pm;
|
|
in_flags[bi] = 0; // no flag is defined at the template entry point
|
|
} else {
|
|
in_regs [bi] = REG_TOP;
|
|
in_pm [bi] = universe_pm;
|
|
in_flags[bi] = FLAG_TOP;
|
|
}
|
|
out_regs [bi] = in_regs [bi] | gen_regs [bi];
|
|
out_pm [bi] = in_pm [bi] | gen_pm [bi];
|
|
out_flags[bi] = in_flags[bi] | gen_flags[bi];
|
|
}
|
|
|
|
// forward must-analysis: in = AND(preds.out); out = in | gen. Iterate to fixpoint.
|
|
bool changed = true;
|
|
while (changed) {
|
|
changed = false;
|
|
for_array(bi, cfg->blocks) {
|
|
if (!cfg->blocks[bi].reachable) {
|
|
continue;
|
|
}
|
|
|
|
u16 nin_r = seed_regs;
|
|
u16 nin_f = 0;
|
|
u64 nin_p = seed_pm;
|
|
if (bi != 0) {
|
|
nin_r = REG_TOP;
|
|
nin_f = FLAG_TOP;
|
|
nin_p = universe_pm;
|
|
for (i32 p : preds[bi]) {
|
|
nin_r &= out_regs[p];
|
|
nin_f &= out_flags[p];
|
|
nin_p &= out_pm[p];
|
|
}
|
|
}
|
|
u16 nout_r = nin_r | gen_regs[bi];
|
|
u64 nout_p = nin_p | gen_pm[bi];
|
|
u16 nout_f = nin_f | gen_flags[bi];
|
|
|
|
if (nin_r != in_regs [bi] ||
|
|
nin_p != in_pm [bi] ||
|
|
nin_f != in_flags [bi] ||
|
|
nout_r != out_regs [bi] ||
|
|
nout_p != out_pm [bi] ||
|
|
nout_f != out_flags[bi]) {
|
|
in_regs [bi] = nin_r;
|
|
in_pm [bi] = nin_p;
|
|
in_flags [bi] = nin_f;
|
|
out_regs [bi] = nout_r;
|
|
out_pm [bi] = nout_p;
|
|
out_flags[bi] = nout_f;
|
|
changed = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
for_array(bi, cfg->blocks) {
|
|
if (!cfg->blocks[bi].reachable) {
|
|
continue;
|
|
}
|
|
in_w[bi] = {};
|
|
if (bi == 0) {
|
|
in_w[bi] = entry_seed_w;
|
|
}
|
|
for (i32 idx = 0; idx < ASM_WIDTH_REG_COUNT; idx++) {
|
|
out_w[bi].e[idx] = gb_max(in_w[bi].e[idx], gen_w[bi].e[idx]);
|
|
}
|
|
}
|
|
changed = true;
|
|
while (changed) {
|
|
changed = false;
|
|
for_array(bi, cfg->blocks) {
|
|
if (!cfg->blocks[bi].reachable) {
|
|
continue;
|
|
}
|
|
AsmRegW nin = {};
|
|
AsmRegW nout = {};
|
|
|
|
auto const &pred = preds[bi];
|
|
|
|
if (bi != 0) {
|
|
for (i32 idx = 0; idx < ASM_WIDTH_REG_COUNT; idx++) {
|
|
nin.e[idx] = 64;
|
|
}
|
|
if (pred.count == 0) {
|
|
// unreachable-by-preds guard
|
|
// just zero it out
|
|
nin = {};
|
|
}
|
|
for (i32 p : pred) {
|
|
for (i32 idx = 0; idx < ASM_WIDTH_REG_COUNT; idx++) {
|
|
nin.e[idx] = gb_min(nin.e[idx], out_w[p].e[idx]);
|
|
}
|
|
}
|
|
} else {
|
|
nin = entry_seed_w;
|
|
}
|
|
for (i32 idx = 0; idx < ASM_WIDTH_REG_COUNT; idx++) {
|
|
nout.e[idx] = gb_max(nin.e[idx], gen_w[bi].e[idx]);
|
|
}
|
|
if (gb_memcompare(&nin, &in_w [bi], gb_size_of(AsmRegW)) != 0 ||
|
|
gb_memcompare(&nout, &out_w[bi], gb_size_of(AsmRegW)) != 0) {
|
|
in_w [bi] = nin;
|
|
out_w[bi] = nout;
|
|
changed = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
// NOTE(bill): publish the register masks and materialise the parameter sets onto the blocks
|
|
for_array(bi, cfg->blocks) {
|
|
AsmBlock *b = &cfg->blocks[bi];
|
|
b->in_defs = in_regs [bi];
|
|
b->out_defs = out_regs [bi];
|
|
b->in_flags = in_flags [bi];
|
|
b->out_flags = out_flags[bi];
|
|
if (!b->reachable) {
|
|
continue;
|
|
}
|
|
for_array(i, decls) {
|
|
Entity *e = decls[i].entity;
|
|
if (e == nullptr) {
|
|
continue;
|
|
}
|
|
if (((in_pm[bi] >> i) & 1) != 0) {
|
|
ptr_set_add(&b->in_params, e);
|
|
}
|
|
if (((out_pm[bi] >> i) & 1) != 0) {
|
|
ptr_set_add(&b->out_params, e);
|
|
}
|
|
}
|
|
}
|
|
{
|
|
auto block_is_targeted = slice_make<bool>(heap_allocator(), cfg->blocks.count);
|
|
defer (slice_free(&block_is_targeted, heap_allocator()));
|
|
|
|
for_array(bi, cfg->blocks) {
|
|
AstAsmInstruction *last = cfg->insts[cfg->blocks[bi].last];
|
|
AsmInstructionFacts *lf = last->facts;
|
|
if (lf != nullptr && lf->branch_target != nullptr) {
|
|
i32 t = asm_cfg_label_block_index(lf->branch_target);
|
|
if (0 <= t && t < cast(i32)cfg->blocks.count) {
|
|
block_is_targeted[t] = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
// NOTE(bill): unreachable code
|
|
for_array(bi, cfg->blocks) {
|
|
AsmBlock const &block = cfg->blocks[bi];
|
|
if (block.reachable) {
|
|
continue;
|
|
}
|
|
AstAsmInstruction *first = cfg->insts[block.first];
|
|
char const *plural = (block.first == block.last) ? "instruction is" : "instructions are";
|
|
if (block_is_targeted[bi]) {
|
|
warning(first->name, "The asm %s unreachable: this block is only reached from code that is itself unreachable", plural);
|
|
} else {
|
|
warning(first->name, "The asm %s unreachable: no branch targets it and control cannot fall through from above (e.g. it follows an unconditional jump, return, or halt)", plural);
|
|
}
|
|
}
|
|
}
|
|
|
|
{ // NOTE(bill): read-before-write, definite-assignment across the whole CFG
|
|
PtrSet<Entity *> reported_params = {};
|
|
defer (ptr_set_destroy(&reported_params));
|
|
|
|
u16 reported_regs = 0;
|
|
u16 reported_flags = 0;
|
|
|
|
for_array(bi, cfg->blocks) {
|
|
AsmBlock const &b = cfg->blocks[bi];
|
|
if (!b.reachable) {
|
|
continue;
|
|
}
|
|
|
|
u16 run_regs = in_regs [bi];
|
|
u16 run_flags = in_flags[bi];
|
|
u64 run_pm = in_pm [bi];
|
|
AsmRegW run_w = in_w [bi];
|
|
|
|
|
|
for (i32 ii = b.first; ii <= b.last; ii++) {
|
|
AstAsmInstruction *instr = cfg->insts[ii];
|
|
AsmInstructionFacts *f = instr->facts;
|
|
if (f == nullptr) {
|
|
continue;
|
|
}
|
|
|
|
u16 undef = f->read_regs & REG_TOP & ~run_regs & ~reported_regs;
|
|
for (u16 bit = 1; bit != 0; bit <<= 1) {
|
|
if ((undef & bit) == 0) {
|
|
continue;
|
|
}
|
|
reported_regs |= bit;
|
|
check_asm_cfg_report_undef_reg(asm_ctx, cfg, entity, instr, f->name, bit);
|
|
}
|
|
|
|
bool is_status_snapshot = false;
|
|
if (instr->mnemonic && instr->valid_form_index >= 0) {
|
|
auto clobber_forms = asm_ctx->clobber_forms(instr->mnemonic);
|
|
if (clobber_forms.count > 0 && instr->valid_form_index < clobber_forms.count) {
|
|
auto &clobber = clobber_forms[instr->valid_form_index];
|
|
is_status_snapshot = clobber.is_status_snapshot();
|
|
}
|
|
}
|
|
|
|
u16 undef_flags = f->read_flags & ~run_flags & ~reported_flags;
|
|
if (is_status_snapshot) {
|
|
undef_flags = 0;
|
|
}
|
|
if (undef_flags != 0) {
|
|
reported_flags |= undef_flags;
|
|
|
|
gbString flag_strs = gb_string_make(heap_allocator(), "");
|
|
defer (gb_string_free(flag_strs));
|
|
|
|
isize count = 0;
|
|
for (u16 bit = 1; bit != 0; bit <<= 1) {
|
|
if (bit & undef_flags) {
|
|
if (count++ > 0) {
|
|
flag_strs = gb_string_appendc(flag_strs, ", ");
|
|
}
|
|
char const *f = asm_ctx->clobber_flag_bit_name(bit);
|
|
flag_strs = gb_string_appendc(flag_strs, "%flags.");
|
|
flag_strs = gb_string_appendc(flag_strs, f);
|
|
}
|
|
}
|
|
|
|
char const *plural = "a status flag";
|
|
if (count > 0) {
|
|
plural = "status flags";
|
|
}
|
|
|
|
error(instr->name,
|
|
"'%.*s' reads %s (%s) that is not set on all paths reaching here; "
|
|
"a flag-setting instruction (e.g. 'cmp', 'test') must precede it on every path",
|
|
LIT(f->name), plural, flag_strs);
|
|
}
|
|
|
|
// Sub-register width
|
|
for (i32 w_idx = 0; w_idx < ASM_WIDTH_REG_COUNT; w_idx++) {
|
|
u8 rw = f->read_reg_w.e[w_idx];
|
|
if (rw == 0) {
|
|
continue;
|
|
}
|
|
u16 bit = cast(u16)(1u << w_idx);
|
|
if ((reported_regs & bit) != 0) {
|
|
continue;
|
|
}
|
|
if (run_w.e[w_idx] < rw) {
|
|
reported_regs |= bit;
|
|
|
|
char const *rname = asm_ctx->clobber_reg_bit_name(bit);
|
|
error(instr->name,
|
|
"'%.*s' reads %s at %u-bit width but only its low %u bits are defined on all paths here; "
|
|
"write the full register first (e.g. zero-extend, or a full-width or 32-bit-zeroing write)",
|
|
LIT(f->name), rname, cast(unsigned)rw, cast(unsigned)run_w.e[w_idx]);
|
|
}
|
|
}
|
|
|
|
for (Entity *pe : f->read_params) {
|
|
i32 *ix = map_get(&cfg->entity_to_index, pe);
|
|
if (ix == nullptr) {
|
|
continue;
|
|
}
|
|
if (((run_pm >> *ix) & 1) == 0 && !ptr_set_exists(&reported_params, pe)) {
|
|
Ast *loc = instr->name;
|
|
for (Ast *op : instr->operands) {
|
|
if (entity_of_node(op) == pe) {
|
|
loc = op;
|
|
break;
|
|
}
|
|
}
|
|
error(loc, "'%.*s' reads '%.*s' before it is assigned; its initial value is undefined", LIT(f->name), LIT(pe->token.string));
|
|
ptr_set_add(&reported_params, pe);
|
|
}
|
|
}
|
|
|
|
run_regs |= f->gen_regs;
|
|
run_flags |= f->gen_flags;
|
|
for (i32 w_idx = 0; w_idx < ASM_WIDTH_REG_COUNT; w_idx++) {
|
|
u8 gw = f->gen_reg_w.e[w_idx];
|
|
if (gw != 0) {
|
|
run_w.e[w_idx] = asm_reg_def_width_after(run_w.e[w_idx], gw);
|
|
}
|
|
}
|
|
for (Entity *pe : f->gen_params) {
|
|
run_pm |= bit_of(pe);
|
|
}
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
{ // NOTE(bill): Collect the template's return points reachable blocks that leave via the end
|
|
u16 exit_regs = REG_TOP;
|
|
u64 exit_pm = universe_pm;
|
|
u16 exit_flags = FLAG_TOP;
|
|
bool any_exit = false;
|
|
for_array(bi, cfg->blocks) {
|
|
if (!cfg->blocks[bi].reachable) {
|
|
continue;
|
|
}
|
|
if (!check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
|
|
continue;
|
|
}
|
|
any_exit = true;
|
|
exit_regs &= out_regs [bi];
|
|
exit_pm &= out_pm [bi];
|
|
exit_flags &= out_flags[bi];
|
|
}
|
|
|
|
// NOTE(bill): Outputs must be assigned on every path that returns
|
|
if (any_exit && !diverging) {
|
|
for_array(i, decls) {
|
|
auto const &ed = decls[i];
|
|
if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) {
|
|
continue;
|
|
}
|
|
if (ed.tie >= 0 || ed.no_init) {
|
|
continue;
|
|
}
|
|
|
|
bool written = false;
|
|
u16 flag_bit = asm_decl_resolve_flag_bit(asm_ctx, ed);
|
|
u16 reg_bit = cfg->decl_pin_bit[i];
|
|
if (flag_bit != 0) {
|
|
// Flag-pinned output: defined iff the pinned flag is set on every returning path.
|
|
written = (exit_flags & flag_bit) != 0;
|
|
} else if (reg_bit != 0) {
|
|
written = (exit_regs & reg_bit) != 0;
|
|
} else {
|
|
written = (exit_pm & bit_of(ed.entity)) != 0;
|
|
}
|
|
if (!written) {
|
|
error(ed.entity->token,
|
|
"'asm' output parameter '%.*s' is not assigned on all paths through this template; "
|
|
"its value is undefined",
|
|
LIT(ed.entity->token.string));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (diverging) { // No reachable path may return / fall off the end
|
|
bool any_leak = false;
|
|
for_array(bi, cfg->blocks) {
|
|
if (cfg->blocks[bi].reachable && check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
|
|
any_leak = true;
|
|
break;
|
|
}
|
|
}
|
|
if (any_leak) {
|
|
error(entity->token,
|
|
"This 'asm' template is declared diverging (-> !) but a reachable path can fall through the end; "
|
|
"end every path with an unconditional jump, return, or halt");
|
|
}
|
|
} else {
|
|
// Not declared diverging: no reachable block leaves => control never returns
|
|
bool any_exit = false;
|
|
for_array(bi, cfg->blocks) {
|
|
auto const &block = cfg->blocks[bi];
|
|
if (block.reachable && check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
|
|
any_exit = true;
|
|
break;
|
|
}
|
|
}
|
|
if (!any_exit) {
|
|
// Distinguish an unconditional self-loop (jmp to own block, no other exit edge)
|
|
// from the general no-returning-path case.
|
|
i32 self_loop_bi = -1;
|
|
for_array(bi, cfg->blocks) {
|
|
AsmBlock const &b = cfg->blocks[bi];
|
|
if (!b.reachable) {
|
|
continue;
|
|
}
|
|
bool loops_to_self = false;
|
|
for (i32 s : b.succs) {
|
|
if (s == cast(i32)bi) {
|
|
loops_to_self = true;
|
|
break;
|
|
}
|
|
}
|
|
if (loops_to_self && b.succs.count == 1) {
|
|
self_loop_bi = cast(i32)bi;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (self_loop_bi >= 0) {
|
|
AstAsmInstruction *first = cfg->insts[cfg->blocks[self_loop_bi].first];
|
|
error(first->name,
|
|
"This asm instruction forms an unconditional self-loop and can never exit; "
|
|
"if the template is meant never to return, declare it diverging (-> !)");
|
|
} else {
|
|
error(entity->token,
|
|
"This 'asm' template has no reachable path that returns or falls through the end; "
|
|
"if this is intended, declare it diverging (-> !)");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Backward liveness: a value is live at a point if some path from there reads it before overwriting it.
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// Dual of the forward definite-assignment pass.
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// Used to find dead writes (a definition never read before being overwritten or before template exit).
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//
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// NOTE(bill): only set `emit_dead_writes` to be true when all instructions are "good".
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template <typename AsmCtx>
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gb_internal bool check_asm_cfg_liveness(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *entity, bool emit_dead_writes) {
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isize const n = cfg->blocks.count;
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if (n == 0) {
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return false;
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}
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u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED;
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u16 exit_live = 0;
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u16 output_regs = 0;
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for_array(i, entity->AsmTemplate.decls) {
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auto const &ed = entity->AsmTemplate.decls[i];
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if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output) {
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exit_live |= cfg->decl_pin_bit[i]; // pinned/view-inherited output reg, if any
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output_regs |= cfg->decl_pin_bit[i];
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}
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}
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for (String const ® : entity->AsmTemplate.clobber_registers_set) {
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exit_live |= asm_ctx->clobber_bit_for_reg_name(reg);
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}
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|
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auto live_in = slice_make<u16>(heap_allocator(), n); defer (slice_free(&live_in, heap_allocator()));
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auto live_out = slice_make<u16>(heap_allocator(), n); defer (slice_free(&live_out, heap_allocator()));
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|
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bool changed = true;
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while (changed) {
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changed = false;
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// Iterate in reverse for faster convergence
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for (isize bi = n - 1; bi >= 0; bi--) {
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if (!cfg->blocks[bi].reachable) {
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continue;
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}
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AsmBlock const &b = cfg->blocks[bi];
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|
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// live_out = union of successors' live_in, plus exit_live if this block leaves.
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u16 lo = 0;
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for (i32 s : b.succs) {
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if (0 <= s && s < cast(i32)n && cfg->blocks[s].reachable) {
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lo |= live_in[s];
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}
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}
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if (check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
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lo |= exit_live;
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}
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|
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u16 live = lo;
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|
for (i32 ii = b.last; ii >= b.first; ii--) {
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AsmInstructionFacts *f = cfg->insts[ii]->facts;
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if (f == nullptr) {
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|
continue;
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|
}
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live = (live & ~asm_full_kill_mask(f)) | (f->read_regs & REG_TOP);
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}
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|
|
|
if (lo != live_out[bi] || live != live_in[bi]) {
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|
live_out[bi] = lo;
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|
live_in[bi] = live;
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|
changed = true;
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|
}
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|
}
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|
}
|
|
|
|
for_array(bi, cfg->blocks) {
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|
cfg->blocks[bi].live_in_regs = live_in[bi];
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|
cfg->blocks[bi].live_out_regs = live_out[bi];
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|
}
|
|
|
|
if (!emit_dead_writes) {
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|
// Lattice has been computed but no diagnostic until the read facts are validated
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|
return false;
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|
}
|
|
|
|
// Dead-write detection: walk each block forward, tracking live-out per instruction.
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|
// A written reg that is not live immediately after the write (and not re-read in
|
|
// this same instruction) is dead.
|
|
for_array(bi, cfg->blocks) {
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|
AsmBlock const &b = cfg->blocks[bi];
|
|
if (!b.reachable) {
|
|
continue;
|
|
}
|
|
// recompute per-instruction live-out by replaying the transfer from block live_out
|
|
// (cheap: block is short). Build an array of live-after-each-instruction.
|
|
u16 live = live_out[bi];
|
|
if (check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
|
|
live |= exit_live; // already folded above, but harmless
|
|
}
|
|
for (i32 ii = b.last; ii >= b.first; ii--) {
|
|
AsmInstructionFacts *f = cfg->insts[ii]->facts;
|
|
if (f == nullptr) {
|
|
continue;
|
|
}
|
|
u16 live_after = live;
|
|
// A register this instruction writes but that is not live afterward,
|
|
// and that it does not itself read (self-use like `xor r,r` or `add r,x`) is a dead write.
|
|
u16 kill = asm_full_kill_mask(f);
|
|
u16 dead = kill & ~live_after & ~f->read_regs;
|
|
for (u16 bit = 1; bit != 0; bit <<= 1) {
|
|
if ((dead & bit) == 0) {
|
|
continue;
|
|
}
|
|
if ((bit & output_regs) != 0) {
|
|
warning(f->node->name,
|
|
"'%.*s' writes output register %%%s, but that value is overwritten before the template returns; "
|
|
"the output's final value does not come from this instruction",
|
|
LIT(f->name), asm_ctx->clobber_reg_bit_name(bit));
|
|
} else {
|
|
warning(f->node->name,
|
|
"'%.*s' writes %%%s but its value is never read before being overwritten or the template ends",
|
|
LIT(f->name), asm_ctx->clobber_reg_bit_name(bit));
|
|
}
|
|
}
|
|
live = (live & ~kill) | (f->read_regs & REG_TOP);
|
|
}
|
|
}
|
|
|
|
return true;
|
|
} |