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Brendan PunskyandClaude Opus 5.5
61314729cb
The A32 Advanced SIMD rows were written out by hand, one mnemonic at a
time, and it showed: most mnemonics had one element size where the
architecture has three or four, masks left the size and the Q bit free,
so one word decoded as whichever row sorted first, the shift-by-immediate
family read the element size as part of the shift, and the element and
structure loads knew neither alignment nor writeback. Against llvm, 1243
random A32 words decoded where llvm decodes nothing and 139 decoded to
the wrong instruction.
Those rows are gone. tablegen/simd_table.odin describes the space the
way the Architecture Reference Manual lays it out -- three registers of
the same length, of different lengths, by scalar, by shift, two-register
miscellaneous, modified immediate, the loads and stores, the v8.x dot
product, complex, FHM, BFloat16 and matrix additions -- and expands each
class into a row per element size, data type and register shape. The
size and type are fixed bits of every row, so a word decodes to one
`.<dt>` and the encoder picks the row by it. The Thumb forms follow
from these as they did before.
The fields whose meaning depends on the rest of the word -- a structure
load's register count, spacing, lane and alignment; L:imm6, whose
leading one is the element size and the rest the shift -- are read off
the whole word (simd.odin), by the decoder from the word and by the
encoder from the form. That replaces thirty-eight per-size encodings
with twelve. Memory gains an alignment (`[r0:64]`) and a post-increment
mode (`[r0]!`), the Advanced SIMD loads' writeback; disp gives up three
of its nineteen bits for it.
Along the way:
* The decoder reused one Instruction across candidate rows, so a row
turned away after unpacking left its operands for the next one: an
LDC2 picked up a fourth operand from a VCMLA it was not.
* VMRS and VMSR reach different system registers per profile; a
register run that is empty or passes D31 is not an instruction;
VDUP from a core register had one size of three and left its
should-be-zero bits free; FLDMX and FSTMX start in D0-D15; SWP's
address is an address; MSR names its PSR fields instead of a
number; PSB CSYNC is AArch64's, and in AArch32 is HINT #17.
* `vmov.i8` is the byte, not four copies of it.
The harness had one blind spot of its own: a literal load's address in
llvm's trailing comment stopped it from asking whether llvm's text
reassembles. And llvm prints a D list that runs past D31 with the names
of the registers after D31 in its own table -- `{d31, fpinst2}` -- and
takes that back; the harness counts that word as having no text, which
is what it is.
The random A32 suite now passes outright: of 42,408 words none decodes
wrong, extra, missing or unassemblable, and every one re-encodes. The
Cortex-A15 and A53 objects, which had 150 Advanced SIMD words rexcode
could not decode, are exact.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01BbUtG4UwNiMydtMW2qGhw4