From d838add05c753cf24208fe214e7fc80ffa8d3598 Mon Sep 17 00:00:00 2001
From: Matthew Leach <dev@mattleach.net>
Date: Thu, 19 Mar 2026 21:52:41 +0000
Subject: [PATCH] arm64: secondary: insert isb after cache flush

Insert an instruction barrier to ensure that the cache-flush operation has
completed prior to the PSCI call.
---
 src/arch/arm64/boot/secondary.rs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/arch/arm64/boot/secondary.rs b/src/arch/arm64/boot/secondary.rs
index e8658a8..20b3c1d 100644
--- a/src/arch/arm64/boot/secondary.rs
+++ b/src/arch/arm64/boot/secondary.rs
@@ -15,6 +15,7 @@ use crate::{
     memory::PAGE_ALLOC,
     sync::OnceLock,
 };
+use aarch64_cpu::asm::barrier::{SY, isb};
 use core::{
     arch::naked_asm,
     hint::spin_loop,
@@ -140,6 +141,8 @@ fn prepare_for_secondary_entry() -> Result<(PA, PA)> {
         // MMU enabled (and therefore caches), we can't reply on the CCI.
         // Therefore, manually flush the boot context to RAM.
         flush_to_ram(boot_ctx);
+
+        isb(SY);
     };
 
     Ok((entry_fn, ctx))