diff --git a/changelog/unreleased/fix-unaligned-atomic-operation-on-arm32.md b/changelog/unreleased/fix-unaligned-atomic-operation-on-arm32.md
new file mode 100644
index 0000000000..8ddbc2b5b2
--- /dev/null
+++ b/changelog/unreleased/fix-unaligned-atomic-operation-on-arm32.md
@@ -0,0 +1,7 @@
+Bugfix: Fixes "unaligned 64-bit atomic operation" panic on 32-bit ARM
+
+sync/cache had uint64s that were not 64-bit aligned causing panics
+on 32-bit systems during atomic access
+
+https://github.com/owncloud/ocis/pull/1888
+https://github.com/owncloud/ocis/issues/1887
diff --git a/ocis-pkg/sync/cache.go b/ocis-pkg/sync/cache.go
index 0ffddf56b7..e63690b35d 100644
--- a/ocis-pkg/sync/cache.go
+++ b/ocis-pkg/sync/cache.go
@@ -8,10 +8,11 @@ import (
 
 // Cache is a barebones cache implementation.
 type Cache struct {
+	// capacity and length have to be the first words
+	// in order to be 64-aligned on 32-bit architectures.
+	capacity, length uint64 // access atomically
 	entries  sync.Map
 	pool     sync.Pool
-	capacity uint64
-	length   uint64
 }
 
 // CacheEntry represents an entry on the cache. You can type assert on V.