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19 lines
926 B
Plaintext
19 lines
926 B
Plaintext
/*
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* GENERATED FILE - DO NOT EDIT
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* (c) Code Red Technologies Ltd, 2008-2013
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* (c) NXP Semiconductors 2013-2018
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* Generated linker script file for MIMXRT1052xxxxB
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* Created from memory.ldt by FMCreateLinkMemory
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v10.2.0 [Build 759] [2018-05-15] on 2018-07-30 10:43:20
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*/
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MEMORY
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{
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/* Define each memory region */
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SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */
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/*SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x0*/ /* 0K bytes (alias RAM2) */
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SRAM_DTC_TEXT (rwx) : ORIGIN = 0x20000000, LENGTH = 0x6000 /* 24K bytes (alias RAM3) */
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SRAM_DTC (rwx) : ORIGIN = 0x20006000, LENGTH = 0x6A000 /* 434K bytes (alias RAM3) */
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BOARD_SDRAM_TEXT (rx) : ORIGIN = 0x80000000, LENGTH = 0x0400000 /* 4M bytes for application code */
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BOARD_SDRAM_HEAP (rwx) : ORIGIN = 0x80400000, LENGTH = 0x0D00000 /* 13M bytes for heap (alias RAM4) */
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} |