mirror of
https://github.com/mudita/MuditaOS.git
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36be49c15b
* [EGD-3046] fix HF handler added boot reason printing and clearing * [EGD-3046] added prining of GPR_5 on checking boot reason * [EGD-3046] added halt if debugging * [EGD-3046] halt if debugging only in exit * [EGD-3046] rename * [EGD-3046] added DEBUG check * [EGD-3046] fixed formatting * [EGD-3046] fixed includes
203 lines
8.8 KiB
C++
203 lines
8.8 KiB
C++
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/*
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* @file board.cpp
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* @author Mateusz Piesta (mateusz.piesta@mudita.com)
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* @date 20.05.19
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* @brief
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* @copyright Copyright (C) 2019 mudita.com
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* @details
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*/
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#include "board.h"
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extern "C"
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{
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#include "fsl_common.h"
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#include "fsl_clock.h"
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#include "fsl_dcdc.h"
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#include "pin_mux.h"
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#if LOG_REDIRECT == RTT_LUART
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#include "fsl_lpuart.h"
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#endif
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}
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#include "chip.hpp"
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#include "irq/irq_gpio.hpp"
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namespace bsp
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{
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#if LOG_REDIRECT == RTT_LUART
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static lpuart_handle_t g_lpuartHandle;
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#endif
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/* Get debug console frequency. */
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__attribute__((unused)) static uint32_t BOARD_DebugConsoleSrcFreq(void)
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{
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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{
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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else {
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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return freq;
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}
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/* Initialize debug console. */
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static void BOARD_InitDebugConsole(void)
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{
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#if LOG_REDIRECT == RTT_LUART
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/* The user initialization should be placed here */
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lpuart_config_t lpuartConfig;
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/* Initialize the LPUART. */
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/*
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* lpuartConfig.baudRate_Bps = 115200U;
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* lpuartConfig.parityMode = kLPUART_ParityDisabled;
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* lpuartConfig.stopBitCount = kLPUART_OneStopBit;
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* lpuartConfig.txFifoWatermark = 0;
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* lpuartConfig.rxFifoWatermark = 0;
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* lpuartConfig.enableTx = false;
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* lpuartConfig.enableRx = false;
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*/
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LPUART_GetDefaultConfig(&lpuartConfig);
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lpuartConfig.baudRate_Bps = 115200;
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lpuartConfig.enableTx = true;
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lpuartConfig.enableRx = true;
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LPUART_TransferCreateHandle(LPUART3, &g_lpuartHandle, NULL, NULL);
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LPUART_Init(LPUART3, &lpuartConfig, BOARD_DebugConsoleSrcFreq());
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LPUART_EnableTx(LPUART3, true);
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LPUART_EnableRx(LPUART3, true);
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#endif
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}
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/* MPU configuration. */
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static void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
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SCB_DisableICache();
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}
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
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SCB_DisableDCache();
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
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* API in core_cm7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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* Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner noncache
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* 1 1 0 0 Normal shareable outer and inner noncache
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* 1 0 1 1 Normal not shareable outer and inner write back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
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*/
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/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Setting Memory with Normal type, not shareable, outer/inner write back. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
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#else
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/* Setting Memory with Device type, not shareable, non-cacheable. */
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// TODO: MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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// TODO: MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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#endif
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/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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// CPU doesn't use cache when accessing TCM memories
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/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
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// OCRAM configured as non-cached segment
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/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64KB);
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back
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* BOARD_SDRAM_TEXT
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*/
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
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/* The define sets the cacheable memory to shareable,
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* this suggestion is referred from chapter 2.2.1 Memory regions,
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* types and attributes in Cortex-M7 Devices, Generic User Guide */
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#if defined(SDRAM_IS_SHAREABLE)
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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#else
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/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back
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* BOARD_SDRAM_HEAP
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*/
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MPU->RBAR = ARM_MPU_RBAR(9, 0x80400000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
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#endif
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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void BoardInit(){
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PINMUX_InitBootPins();
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BOARD_InitBootClocks();
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BOARD_ConfigMPU();
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BOARD_InitDebugConsole();
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irq_gpio_Init();
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// Set internal DCDC to DCM mode. Switching between DCM and CCM mode will be done automatically.
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DCDC_BootIntoDCM(DCDC);
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PrintSystemClocks();
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clearAndPrintBootReason();
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}
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} // namespace bsp
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