Reformat the instruction table

core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin

@@ -450,7 +450,7 @@ main :: proc() {
 	strings.write_string(&sb, "\ttypedef u8 EncodingFlags; // cannot use a C++ bit field to due lack of portability\n")
 	strings.write_string(&sb, "\n")
 	{
-		defer strings.write_string(&sb, "\tGB_STATIC_ASSERT(gb_size_of(Encoding) == 20);\n")
+		defer strings.write_string(&sb, "\tGB_STATIC_ASSERT(gb_size_of(Encoding) == 22);\n")
 
 		strings.write_string(&sb, "\t#pragma pack(push, 1)\n")
 		defer strings.write_string(&sb, "\t#pragma pack(pop)\n")
@@ -458,8 +458,8 @@ main :: proc() {
 		defer strings.write_string(&sb, "\t};\n")
 		strings.write_string(&sb, """
 				Mnemonic        mnemonic;
-				OperandType     ops[4];
-				OperandEncoding enc[4];
+				OperandType     ops[5];
+				OperandEncoding enc[5];
 				u32             bits;
 				u32             mask;
 				Feature         feature;
@@ -631,8 +631,6 @@ main :: proc() {
 			// SVE vector + predicate registers.
 			case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D:
 			case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV:
-			// SME2 multi-vector register lists (first register of the list).
-			case OP_Z_PAIR: case OP_Z_QUAD:
 			// SME ZA tiles (ZA0.B .. ZAn.Q) — register-like tile operands.
 			case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S:
 			case OP_ZA_TILE_D: case OP_ZA_TILE_Q:
@@ -700,7 +698,6 @@ main :: proc() {
 			case OP_V_4H_FP16: case OP_V_8H_FP16:
 			case OP_V_ELEM_B: case OP_V_ELEM_H: case OP_V_ELEM_S: case OP_V_ELEM_D:
 			case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D:
-			case OP_Z_PAIR: case OP_Z_QUAD:
 				return AsmRegClass_Vector;
 
 			// SVE predicate registers.
@@ -825,7 +822,6 @@ main :: proc() {
 			// ---- Width is scalable, data-dependent, or set elsewhere -> 0 ----
 			case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: // SVE VL-scaled
 			case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: // predicate (VL/8)
-			case OP_Z_PAIR: case OP_Z_QUAD:                                       // SVE reg-lists (scalable)
 			case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S:
 			case OP_ZA_TILE_D: case OP_ZA_TILE_Q:                                 // SME tiles (scalable)
 			case OP_SME_PATTERN:                                                  // selector, no data width

src/asm_tables.cpp

@@ -31,6 +31,7 @@ enum AsmOperandKind : u8 {
 	AsmOperand_Register_Or_Memory,
 	AsmOperand_Immediate,
 	AsmOperand_Label,
+	AsmOperand_RegisterGroup,
 
 	AsmOperand_COUNT
 };

src/parser.cpp

@@ -558,6 +558,10 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) {
 		n->AsmMemoryOperand.disp  = clone_ast(n->AsmMemoryOperand.disp,  f);
 		n->AsmMemoryOperand.type  = clone_ast(n->AsmMemoryOperand.type,  f);
 		break;
+	case Ast_AsmRegisterGroup:
+		n->AsmRegisterGroup.registers = clone_ast_array(n->AsmRegisterGroup.registers, f);
+		n->AsmRegisterGroup.type      = clone_ast(n->AsmRegisterGroup.type, f);
+		break;
 	case Ast_AsmDirective:
 		n->AsmDirective.operands = clone_ast_array(n->AsmDirective.operands, f);
 		break;
@@ -2573,6 +2577,61 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) {
 			return mem;
 		}
 		break;
+	case Token_OpenBrace:
+		if (allow_memory_operand) {
+			Token open  = expect_token(f, Token_OpenBrace);
+
+			Array<Ast *> registers = {};
+			registers.allocator = heap_allocator();
+			Ast *type = nullptr;
+
+			Ast *first_reg = parse_asm_operand(f, false);
+			Token range_token = {};
+			switch (f->curr_token.kind) {
+			case Token_RangeHalf:
+			case Token_RangeFull:
+				{
+					range_token = advance_token(f);
+					Ast *second_reg = parse_asm_operand(f, false);
+					array_reserve(&registers, 2);
+					array_add(&registers, first_reg);
+					array_add(&registers, second_reg);
+
+					if (allow_token(f, Token_Comma)) {
+						// allow for trailing comma
+					}
+				}
+				break;
+			default:
+				if (allow_token(f, Token_Comma)) {
+					// allow for trailing comma
+				}
+				while (f->curr_token.kind != Token_CloseBrace &&
+				       f->curr_token.kind != Token_EOF) {
+					Ast *reg = parse_asm_operand(f, false);
+					array_add(&registers, reg);
+
+					if (!allow_token(f, Token_Comma)) {
+						break;
+					}
+				}
+				break;
+			}
+			Token close = expect_token(f, Token_CloseBrace);
+			if (allow_token(f, Token_Colon)) {
+				type = parse_type(f);
+			}
+
+			Ast *rg = alloc_ast_node(f, Ast_AsmRegisterGroup);
+			rg->AsmRegisterGroup.open        = open;
+			rg->AsmRegisterGroup.registers   = registers;
+			rg->AsmRegisterGroup.range_token = range_token;
+			rg->AsmRegisterGroup.close       = close;
+			rg->AsmRegisterGroup.type        = type;
+
+			return rg;
+		}
+		break;
 	}
 
 	if (operand == nullptr) {

src/parser.hpp

@@ -525,6 +525,13 @@ struct AstSplitArgs {
 		Ast * type;     \
 		Token close;    \
 	}) \
+	AST_KIND(AsmRegisterGroup, "asm register group", struct { \
+		Token        open;        \
+		Array<Ast *> registers;   \
+		Token        range_token; \
+		Token        close;       \
+		Ast *        type;        \
+	}) \
 	AST_KIND(AsmDirective, "asm directive", struct { \
 		Token        token;    \
 		Token        name;     \

src/parser_pos.cpp

@@ -28,6 +28,8 @@ gb_internal Token ast_token(Ast *node) {
 		return ast_token(node->AsmInstruction.name);
 	case Ast_AsmMemoryOperand:
 		return node->AsmMemoryOperand.open;
+	case Ast_AsmRegisterGroup:
+		return node->AsmRegisterGroup.open;
 	case Ast_AsmDirective:
 		return node->AsmDirective.token;
 
@@ -211,6 +213,11 @@ Token ast_end_token(Ast *node) {
 			return ast_end_token(node->AsmMemoryOperand.type);
 		}
 		return node->AsmMemoryOperand.close;
+	case Ast_AsmRegisterGroup:
+		if (node->AsmRegisterGroup.type) {
+			return ast_end_token(node->AsmRegisterGroup.type);
+		}
+		return node->AsmRegisterGroup.close;
 
 	case Ast_BadExpr:       return node->BadExpr.end;
 	case Ast_TagExpr: