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https://github.com/CalcProgrammer1/OpenRGB.git
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311 lines
8.7 KiB
C++
311 lines
8.7 KiB
C++
/*-------------------------------------------------------------------*\
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| XPGSpectrixS40GController.cpp |
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| Driver for XPG's Spectrix S40G NVMe |
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| NicolasNewman 25th Mar 2021 |
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\*-------------------------------------------------------------------*/
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#include "XPGSpectrixS40GController.h"
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#include <malloc.h>
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#include <cstring>
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#include "LogManager.h"
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/*-----------------------------------------*\
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| AsusAuraSMBusController.cpp |
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| Driver for ASUS Aura RGB lighting |
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| controller |
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| Adam Honse (CalcProgrammer1) 8/19/2018 |
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\*-----------------------------------------*/
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#include <cstring>
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static const char* aura_channels[] = /* Aura channel strings */
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{
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"Audio",
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"Backplate",
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"Back I/O",
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"Center",
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"Center",
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"DRAM",
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"PCIe",
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"RGB Header",
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"RGB Header 2",
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"RGB Header",
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"Unknown",
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};
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XPGSpectrixS40GController::XPGSpectrixS40GController(int fd, aura_dev_id dev)
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{
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nvme_fd = fd;
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this->dev = dev;
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direct_reg = AURA_REG_COLORS_DIRECT_V2;
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effect_reg = AURA_REG_COLORS_EFFECT_V2;
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channel_cfg = AURA_CONFIG_CHANNEL_V2;
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led_count = 8;
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}
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XPGSpectrixS40GController::~XPGSpectrixS40GController()
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{
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}
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std::string XPGSpectrixS40GController::GetDeviceName()
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{
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return("SSD");
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}
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std::string XPGSpectrixS40GController::GetDeviceLocation()
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{
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return("I2C: SSD");
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}
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unsigned char XPGSpectrixS40GController::GetChannel(unsigned int led)
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{
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return(0);
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}
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const char * XPGSpectrixS40GController::GetChannelName(unsigned int led)
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{
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switch (config_table[channel_cfg + led])
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{
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case (unsigned char)AURA_LED_CHANNEL_AUDIO:
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return(aura_channels[0]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_BACKPLATE:
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return(aura_channels[1]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_BACK_IO:
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return(aura_channels[2]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_CENTER:
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return(aura_channels[3]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_CENTER_START:
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return(aura_channels[4]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_DRAM:
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return(aura_channels[5]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_PCIE:
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return(aura_channels[6]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_RGB_HEADER:
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return(aura_channels[7]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_RGB_HEADER_2:
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return(aura_channels[8]);
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break;
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case (unsigned char)AURA_LED_CHANNEL_RGB_HEADER_3:
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return(aura_channels[9]);
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break;
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default:
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return(aura_channels[10]);
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break;
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}
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}
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unsigned int XPGSpectrixS40GController::GetLEDCount()
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{
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return(led_count);
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}
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unsigned char XPGSpectrixS40GController::GetLEDRed(unsigned int led)
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{
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return(AuraRegisterRead(direct_reg + ( 3 * led )));
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}
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unsigned char XPGSpectrixS40GController::GetLEDGreen(unsigned int led)
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{
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return(AuraRegisterRead(direct_reg + ( 3 * led ) + 2));
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}
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unsigned char XPGSpectrixS40GController::GetLEDBlue(unsigned int led)
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{
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return(AuraRegisterRead(direct_reg + ( 3 * led ) + 1));
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}
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void XPGSpectrixS40GController::SaveMode()
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{
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AuraRegisterWrite(AURA_REG_APPLY, AURA_SAVE_VAL);
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}
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void XPGSpectrixS40GController::SetAllColorsDirect(RGBColor* colors)
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{
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unsigned char* color_buf = new unsigned char[led_count * 3];
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for (unsigned int i = 0; i < (led_count * 3); i += 3)
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{
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color_buf[i + 0] = RGBGetRValue(colors[i / 3]);
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color_buf[i + 1] = RGBGetBValue(colors[i / 3]);
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color_buf[i + 2] = RGBGetGValue(colors[i / 3]);
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}
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AuraRegisterWriteBlock(direct_reg, color_buf, led_count * 3);
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delete color_buf;
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}
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void XPGSpectrixS40GController::SetAllColorsEffect(RGBColor* colors)
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{
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unsigned char* color_buf = new unsigned char[led_count * 3];
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for (unsigned int i = 0; i < (led_count * 3); i += 3)
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{
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color_buf[i + 0] = RGBGetRValue(colors[i / 3]);
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color_buf[i + 1] = RGBGetBValue(colors[i / 3]);
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color_buf[i + 2] = RGBGetGValue(colors[i / 3]);
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}
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AuraRegisterWriteBlock(effect_reg, color_buf, led_count * 3);
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AuraRegisterWrite(AURA_REG_APPLY, AURA_APPLY_VAL);
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delete[] color_buf;
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}
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void XPGSpectrixS40GController::SetDirect(unsigned char direct)
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{
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AuraRegisterWrite(AURA_REG_DIRECT, direct);
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AuraRegisterWrite(AURA_REG_APPLY, AURA_APPLY_VAL);
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}
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void XPGSpectrixS40GController::SetLEDColorDirect(unsigned int led, unsigned char red, unsigned char green, unsigned char blue)
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{
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unsigned char colors[3] = { red, blue, green };
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AuraRegisterWriteBlock(direct_reg + ( 3 * led ), colors, 3);
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}
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void XPGSpectrixS40GController::SetLEDColorEffect(unsigned int led, unsigned char red, unsigned char green, unsigned char blue)
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{
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unsigned char colors[3] = { red, blue, green };
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AuraRegisterWriteBlock(effect_reg + (3 * led), colors, 3);
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AuraRegisterWrite(AURA_REG_APPLY, AURA_APPLY_VAL);
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}
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void XPGSpectrixS40GController::SetMode(unsigned char mode, unsigned char speed, unsigned char direction)
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{
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AuraRegisterWrite(AURA_REG_MODE, mode);
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AuraRegisterWrite(AURA_REG_SPEED, speed);
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AuraRegisterWrite(AURA_REG_DIRECTION, direction);
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AuraRegisterWrite(AURA_REG_APPLY, AURA_APPLY_VAL);
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}
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void XPGSpectrixS40GController::AuraUpdateDeviceName()
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{
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for (int i = 0; i < 16; i++)
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{
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device_name[i] = AuraRegisterRead(AURA_REG_DEVICE_NAME + i);
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}
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}
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unsigned char XPGSpectrixS40GController::AuraRegisterRead(aura_register reg)
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{
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return(0);
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}
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void XPGSpectrixS40GController::AuraRegisterWrite(aura_register reg, unsigned char val)
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{
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struct xpg_nvme_command cfg =
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{
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.opcode = 0,
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.flags = 0,
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.rsvd = 0,
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.namespace_id = 0,
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.data_len = 0,
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.metadata_len = 0,
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.timeout = 0,
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.cdw2 = 0,
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.cdw3 = 0,
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.cdw10 = 0,
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.cdw11 = 0,
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.cdw12 = 0,
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.cdw13 = 0,
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.cdw14 = 0,
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.cdw15 = 0,
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};
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unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
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cfg.opcode = 0xFB;
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cfg.namespace_id = 0x00000031;
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cfg.cdw12 = (corrected_reg << 16) | (dev << 1);
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cfg.cdw13 = 0x01100001;
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cfg.data_len = 1;
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cfg.write = true;
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unsigned char data[1];
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data[0] = val;
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unsigned char metadata[1];
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unsigned int result;
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/*-----------------------------------------------------------------------------*\
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| Send the command to the device |
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\*-----------------------------------------------------------------------------*/
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nvme_admin_passthru(nvme_fd, cfg.opcode, cfg.flags, cfg.rsvd,
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cfg.namespace_id, cfg.cdw2, cfg.cdw3, cfg.cdw10,
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cfg.cdw11, cfg.cdw12, cfg.cdw13, cfg.cdw14,
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cfg.cdw15, cfg.data_len, data, cfg.metadata_len,
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metadata, cfg.timeout, &result);
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}
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void XPGSpectrixS40GController::AuraRegisterWriteBlock(aura_register reg, unsigned char * data, unsigned char sz)
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{
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struct xpg_nvme_command cfg =
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{
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.opcode = 0,
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.flags = 0,
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.rsvd = 0,
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.namespace_id = 0,
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.data_len = 0,
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.metadata_len = 0,
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.timeout = 0,
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.cdw2 = 0,
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.cdw3 = 0,
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.cdw10 = 0,
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.cdw11 = 0,
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.cdw12 = 0,
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.cdw13 = 0,
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.cdw14 = 0,
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.cdw15 = 0,
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};
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unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
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cfg.opcode = 0xFB;
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cfg.namespace_id = 0x00000031;
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cfg.cdw12 = (corrected_reg << 16) | (dev << 1);
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cfg.cdw13 = 0x03100000 | sz;
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cfg.data_len = sz;
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unsigned char metadata[1];
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unsigned int result;
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/*-----------------------------------------------------------------------------*\
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| Send the command to the device |
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\*-----------------------------------------------------------------------------*/
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nvme_admin_passthru(nvme_fd, cfg.opcode, cfg.flags, cfg.rsvd,
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cfg.namespace_id, cfg.cdw2, cfg.cdw3, cfg.cdw10,
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cfg.cdw11, cfg.cdw12, cfg.cdw13, cfg.cdw14,
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cfg.cdw15, cfg.data_len, data, cfg.metadata_len,
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metadata, cfg.timeout, &result);
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}
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