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Minor cleanup

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This commit is contained in:
Adam Honse
2021-11-16 21:07:24 -06:00
parent a11c31e376
commit fef63b4626
3 changed files with 91 additions and 280 deletions
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309
Controllers/XPGSpectrixS40GControllerLinux/XPGSpectrixS40GController.cpp
View File

@@ -219,178 +219,10 @@ unsigned char XPGSpectrixS40GController::AuraRegisterRead(aura_register reg)
return(0);
}
#include "libnvme.h"
void XPGSpectrixS40GController::AuraRegisterWrite(aura_register reg, unsigned char val)
{
struct config {
__u8 opcode;
__u8 flags;
__u16 rsvd;
__u32 namespace_id;
__u32 data_len;
__u32 metadata_len;
__u32 timeout;
__u32 cdw2;
__u32 cdw3;
__u32 cdw10;
__u32 cdw11;
__u32 cdw12;
__u32 cdw13;
__u32 cdw14;
__u32 cdw15;
char *input_file;
int raw_binary;
int show_command;
int dry_run;
int read;
int write;
__u8 prefill;
int latency;
};
struct config cfg = {
.opcode = 0,
.flags = 0,
.rsvd = 0,
.namespace_id = 0,
.data_len = 0,
.metadata_len = 0,
.timeout = 10,
.cdw2 = 0,
.cdw3 = 0,
.cdw10 = 0,
.cdw11 = 0,
.cdw12 = 0,
.cdw13 = 0,
.cdw14 = 0,
.cdw15 = 0,
.input_file = "",
.prefill = 0,
};
unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
cfg.opcode = 0xFB;
cfg.namespace_id = 0x00000031;
cfg.cdw12 = (corrected_reg << 16) | (dev << 1);
cfg.cdw13 = 0x01100001;
cfg.data_len = 1;
cfg.write = true;
unsigned char data[1];
data[0] = val;
unsigned char metadata[1];
unsigned int result;
nvme_admin_passthru(nvme_fd, cfg.opcode, cfg.flags, cfg.rsvd,
cfg.namespace_id, cfg.cdw2, cfg.cdw3, cfg.cdw10,
cfg.cdw11, cfg.cdw12, cfg.cdw13, cfg.cdw14,
cfg.cdw15, cfg.data_len, data, cfg.metadata_len,
metadata, cfg.timeout, &result);
// if(hDevice != INVALID_HANDLE_VALUE)
// {
// /*-----------------------------------------------------------------------------*\
// | Create buffer to hold STORAGE_PROTOCOL_COMMAND |
// | Size must be enough for the STORAGE_PROTOCOL_COMMAND struct plus the command |
// | data. Subtract sizeof(DWORD) as the Command field in the structure overlaps |
// | the actual command data. |
// \*-----------------------------------------------------------------------------*/
// unsigned char buffer[sizeof(STORAGE_PROTOCOL_COMMAND) + (sizeof(DWORD) * 34) - sizeof(DWORD)];
// /*-----------------------------------------------------------------------------*\
// | Create STORAGE_PROTOCOL_COMMAND pointer and point it to the buffer |
// \*-----------------------------------------------------------------------------*/
// PSTORAGE_PROTOCOL_COMMAND command = (PSTORAGE_PROTOCOL_COMMAND)buffer;
// /*-----------------------------------------------------------------------------*\
// | Fill in STORAGE_PROTOCOL_COMMAND structure |
// \*-----------------------------------------------------------------------------*/
// command->Version = STORAGE_PROTOCOL_STRUCTURE_VERSION;
// command->Length = sizeof(STORAGE_PROTOCOL_COMMAND);
// command->ProtocolType = ProtocolTypeNvme;
// command->Flags = STORAGE_PROTOCOL_COMMAND_FLAG_ADAPTER_REQUEST;
// command->ReturnStatus = 0x00000000;
// command->ErrorCode = 0x00000000;
// command->CommandLength = STORAGE_PROTOCOL_COMMAND_LENGTH_NVME;
// command->ErrorInfoLength = 0x00000040;
// command->DataToDeviceTransferLength = 0x00000001;
// command->DataFromDeviceTransferLength = 0x00000000;
// command->TimeOutValue = 0x00000001;
// command->ErrorInfoOffset = 0x00000090;
// command->DataToDeviceBufferOffset = 0x000000D0;
// command->DataFromDeviceBufferOffset = 0x00000000;
// command->CommandSpecific = STORAGE_PROTOCOL_SPECIFIC_NVME_ADMIN_COMMAND;
// command->Reserved0 = 0x00000000;
// command->FixedProtocolReturnData = 0x00000000;
// command->Reserved1[0] = 0x00000000;
// command->Reserved1[1] = 0x00000000;
// command->Reserved1[2] = 0x00000000;
// /*-----------------------------------------------------------------------------*\
// | Create ENE Register Write command, filling in the appropriate register and |
// | value |
// \*-----------------------------------------------------------------------------*/
// PNVME_COMMAND CommandValue = (PNVME_COMMAND)command->Command;
// unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
// CommandValue->CDW0.OPC = 0xFB;
// CommandValue->NSID = 0x00000031;
// CommandValue->u.GENERAL.CDW12 = (corrected_reg << 16) | (dev << 1);
// CommandValue->u.GENERAL.CDW13 = 0x01100001;
// DWORD ExtraValue[18] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
// 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
// ExtraValue[16] = val;
// /*-----------------------------------------------------------------------------*\
// | Copy the ENE Register Write extra data into the STORAGE_PROTOCOL_COMMAND |
// | buffer |
// \*-----------------------------------------------------------------------------*/
// memcpy(&command->Command + sizeof(NVME_COMMAND), ExtraValue, sizeof(ExtraValue));
// /*-----------------------------------------------------------------------------*\
// | Send the STORAGE_PROTOCOL_COMMAND to the device |
// \*-----------------------------------------------------------------------------*/
// DeviceIoControl(hDevice, IOCTL_STORAGE_PROTOCOL_COMMAND, buffer, sizeof(buffer), buffer, sizeof(buffer), 0x0, (LPOVERLAPPED)0x0);
// }
}
void XPGSpectrixS40GController::AuraRegisterWriteBlock(aura_register reg, unsigned char * data, unsigned char sz)
{
struct config {
__u8 opcode;
__u8 flags;
__u16 rsvd;
__u32 namespace_id;
__u32 data_len;
__u32 metadata_len;
__u32 timeout;
__u32 cdw2;
__u32 cdw3;
__u32 cdw10;
__u32 cdw11;
__u32 cdw12;
__u32 cdw13;
__u32 cdw14;
__u32 cdw15;
char *input_file;
int raw_binary;
int show_command;
int dry_run;
int read;
int write;
__u8 prefill;
int latency;
};
struct config cfg = {
struct xpg_nvme_command cfg =
{
.opcode = 0,
.flags = 0,
.rsvd = 0,
@@ -406,96 +238,73 @@ void XPGSpectrixS40GController::AuraRegisterWriteBlock(aura_register reg, unsign
.cdw13 = 0,
.cdw14 = 0,
.cdw15 = 0,
.input_file = "",
.prefill = 0,
};
unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
cfg.opcode = 0xFB;
cfg.namespace_id = 0x00000031;
cfg.cdw12 = (corrected_reg << 16) | (dev << 1);
cfg.cdw13 = 0x03100000 | sz;
cfg.data_len = sz;
cfg.opcode = 0xFB;
cfg.namespace_id = 0x00000031;
cfg.cdw12 = (corrected_reg << 16) | (dev << 1);
cfg.cdw13 = 0x01100001;
cfg.data_len = 1;
cfg.write = true;
unsigned char metadata[1];
unsigned char data[1];
unsigned int result;
data[0] = val;
unsigned char metadata[1];
unsigned int result;
/*-----------------------------------------------------------------------------*\
| Send the command to the device |
\*-----------------------------------------------------------------------------*/
nvme_admin_passthru(nvme_fd, cfg.opcode, cfg.flags, cfg.rsvd,
cfg.namespace_id, cfg.cdw2, cfg.cdw3, cfg.cdw10,
cfg.cdw11, cfg.cdw12, cfg.cdw13, cfg.cdw14,
cfg.cdw15, cfg.data_len, data, cfg.metadata_len,
metadata, cfg.timeout, &result);
}
void XPGSpectrixS40GController::AuraRegisterWriteBlock(aura_register reg, unsigned char * data, unsigned char sz)
{
struct xpg_nvme_command cfg =
{
.opcode = 0,
.flags = 0,
.rsvd = 0,
.namespace_id = 0,
.data_len = 0,
.metadata_len = 0,
.timeout = 0,
.cdw2 = 0,
.cdw3 = 0,
.cdw10 = 0,
.cdw11 = 0,
.cdw12 = 0,
.cdw13 = 0,
.cdw14 = 0,
.cdw15 = 0,
};
unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
cfg.opcode = 0xFB;
cfg.namespace_id = 0x00000031;
cfg.cdw12 = (corrected_reg << 16) | (dev << 1);
cfg.cdw13 = 0x03100000 | sz;
cfg.data_len = sz;
unsigned char metadata[1];
unsigned int result;
/*-----------------------------------------------------------------------------*\
| Send the command to the device |
\*-----------------------------------------------------------------------------*/
nvme_admin_passthru(nvme_fd, cfg.opcode, cfg.flags, cfg.rsvd,
cfg.namespace_id, cfg.cdw2, cfg.cdw3, cfg.cdw10,
cfg.cdw11, cfg.cdw12, cfg.cdw13, cfg.cdw14,
cfg.cdw15, cfg.data_len, data, cfg.metadata_len,
metadata, cfg.timeout, &result);
// if(hDevice != INVALID_HANDLE_VALUE)
// {
// /*-----------------------------------------------------------------------------*\
// | Create buffer to hold STORAGE_PROTOCOL_COMMAND |
// | Size must be enough for the STORAGE_PROTOCOL_COMMAND struct plus the command |
// | data. Subtract sizeof(DWORD) as the Command field in the structure overlaps |
// | the actual command data. |
// \*-----------------------------------------------------------------------------*/
// unsigned char buffer[sizeof(STORAGE_PROTOCOL_COMMAND) + (sizeof(DWORD) * 39) - sizeof(DWORD)];
// /*-----------------------------------------------------------------------------*\
// | Create STORAGE_PROTOCOL_COMMAND pointer and point it to the buffer |
// \*-----------------------------------------------------------------------------*/
// PSTORAGE_PROTOCOL_COMMAND command = (PSTORAGE_PROTOCOL_COMMAND)buffer;
// /*-----------------------------------------------------------------------------*\
// | Fill in STORAGE_PROTOCOL_COMMAND structure |
// \*-----------------------------------------------------------------------------*/
// command->Version = STORAGE_PROTOCOL_STRUCTURE_VERSION;
// command->Length = sizeof(STORAGE_PROTOCOL_COMMAND);
// command->ProtocolType = ProtocolTypeNvme;
// command->Flags = STORAGE_PROTOCOL_COMMAND_FLAG_ADAPTER_REQUEST;
// command->ReturnStatus = 0x00000000;
// command->ErrorCode = 0x00000000;
// command->CommandLength = STORAGE_PROTOCOL_COMMAND_LENGTH_NVME;
// command->ErrorInfoLength = 0x00000040;
// command->DataToDeviceTransferLength = sz;
// command->DataFromDeviceTransferLength = 0x00000000;
// command->TimeOutValue = 0x00000001;
// command->ErrorInfoOffset = 0x00000090;
// command->DataToDeviceBufferOffset = 0x000000D0;
// command->DataFromDeviceBufferOffset = 0x00000000;
// command->CommandSpecific = STORAGE_PROTOCOL_SPECIFIC_NVME_ADMIN_COMMAND;
// command->Reserved0 = 0x00000000;
// command->FixedProtocolReturnData = 0x00000000;
// command->Reserved1[0] = 0x00000000;
// command->Reserved1[1] = 0x00000000;
// command->Reserved1[2] = 0x00000000;
// /*-----------------------------------------------------------------------------*\
// | Create ENE Register Write Block command, filling in the appropriate register |
// | and value |
// \*-----------------------------------------------------------------------------*/
// PNVME_COMMAND CommandValue = (PNVME_COMMAND)command->Command;
// unsigned short corrected_reg = ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF);
// CommandValue->CDW0.OPC = 0xFB;
// CommandValue->NSID = 0x00000031;
// CommandValue->u.GENERAL.CDW12 = (corrected_reg << 16) | (dev << 1);
// CommandValue->u.GENERAL.CDW13 = 0x03100000 | sz;
// DWORD ExtraValue[23] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
// 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
// 0x00000000, 0x00000000, 0x00000000 };
// memcpy(&ExtraValue[16], data, sz);
// /*-----------------------------------------------------------------------------*\
// | Copy the ENE Register Write Block extra data into the |
// | STORAGE_PROTOCOL_COMMAND buffer |
// \*-----------------------------------------------------------------------------*/
// memcpy(&command->Command + sizeof(NVME_COMMAND), ExtraValue, sizeof(ExtraValue));
// /*-----------------------------------------------------------------------------*\
// | Send the STORAGE_PROTOCOL_COMMAND to the device |
// \*-----------------------------------------------------------------------------*/
// DeviceIoControl(hDevice, IOCTL_STORAGE_PROTOCOL_COMMAND, buffer, sizeof(buffer), buffer, sizeof(buffer), 0x0, (LPOVERLAPPED)0x0);
// }
}

47
Controllers/XPGSpectrixS40GControllerLinux/XPGSpectrixS40GController.h
View File

@@ -12,17 +12,12 @@
#include <hidapi/hidapi.h>
#include <stdint.h>
#include "libnvme.h"
#pragma once
#define XPG_SPECTRIX_LED_COUNT ( 8 )
#ifdef _WIN32
#include <windows.h>
#include <fileapi.h>
#else
#endif
/*-----------------------------------------*\
| AsusAuraSMBusController.h |
| |
@@ -33,7 +28,6 @@
\*-----------------------------------------*/
#include <string>
#include "i2c_smbus.h"
#pragma once
@@ -117,22 +111,33 @@ enum
AURA_CONFIG_CHANNEL_V2 = 0x1B, /* LED Channel V2 configuration offset */
};
struct xpg_nvme_command
{
__u8 opcode;
__u8 flags;
__u16 rsvd;
__u32 namespace_id;
__u32 data_len;
__u32 metadata_len;
__u32 timeout;
__u32 cdw2;
__u32 cdw3;
__u32 cdw10;
__u32 cdw11;
__u32 cdw12;
__u32 cdw13;
__u32 cdw14;
__u32 cdw15;
int read;
int write;
};
class XPGSpectrixS40GController
{
public:
XPGSpectrixS40GController(int fd, aura_dev_id dev);
~XPGSpectrixS40GController();
#ifdef _WIN32
/*-----------------------------------------------------*\
| Windows specific function that allows the devices |
| handle to be passed from elsewhere once detected |
\*-----------------------------------------------------*/
int SetHandle(wchar_t dev_name[MAX_PATH]);
#else
#endif
std::string GetDeviceName();
std::string GetDeviceLocation();
unsigned char GetChannel(unsigned int led);
@@ -156,11 +161,6 @@ public:
void AuraRegisterWriteBlock(aura_register reg, unsigned char * data, unsigned char sz);
private:
#ifdef _WIN32
HANDLE hDevice;
#else
#endif
int nvme_fd;
char device_name[16];
unsigned char config_table[64];
@@ -168,7 +168,6 @@ private:
aura_register direct_reg;
aura_register effect_reg;
unsigned char channel_cfg;
i2c_smbus_interface * bus;
aura_dev_id dev;
};

15
Controllers/XPGSpectrixS40GControllerLinux/XPGSpectrixS40GControllerDetect.cpp
View File

@@ -21,15 +21,18 @@
void DetectSpectrixS40GControllers(std::vector<RGBController*>& rgb_controllers)
{
XPGSpectrixS40GController* new_xpg_s40g;
RGBController_XPGSpectrixS40G* new_controller;
XPGSpectrixS40GController* new_controller;
RGBController_XPGSpectrixS40G* new_rgbcontroller;
int nvme_fd = open("/dev/nvme0", O_RDWR);
new_xpg_s40g = new XPGSpectrixS40GController(nvme_fd, 0x67);
new_controller = new RGBController_XPGSpectrixS40G(new_xpg_s40g);
rgb_controllers.push_back(new_controller);
if(nvme_fd > 0)
{
new_controller = new XPGSpectrixS40GController(nvme_fd, 0x67);
new_rgbcontroller = new RGBController_XPGSpectrixS40G(new_controller);
rgb_controllers.push_back(new_rgbcontroller);
}
} /* DetectSpectrixS40GControllers() */