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Unlock 0x8B5 register macro guard for SX162 (#9777)

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Ben Meadors
2026-02-28 08:38:08 -06:00
committed by GitHub
parent c28bdbd7e6
commit 43aa90fc3f
1 changed files with 2 additions and 5 deletions
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7
src/mesh/SX126xInterface.cpp
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@@ -194,16 +194,13 @@ template <typename T> bool SX126xInterface<T>::init()
LOG_INFO("Set RX gain to power saving mode (boosted mode off); result: %d", result);
}
#ifdef USE_GC1109_PA
// Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity
// on boards with the GC1109 FEM. Sets bit 0 of register 0x8B5.
// Reference: https://github.com/meshcore-dev/MeshCore/pull/1398
// Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity.
// Sets bit 0 of register 0x8B5.
if (module.SPIsetRegValue(0x8B5, 0x01, 0, 0) == RADIOLIB_ERR_NONE) {
LOG_INFO("Applied SX1262 register 0x8B5 patch for GC1109 RX improvement");
} else {
LOG_WARN("Failed to apply SX1262 register 0x8B5 patch for GC1109");
}
#endif
#if 0
// Read/write a register we are not using (only used for FSK mode) to test SPI comms