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Apply SX1262 register 0x8B5 patch for improved GC1109 RX sensitivity (#9571)

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* Apply SX1262 register 0x8B5 patch for improved GC1109 RX sensitivity

Sets the LSB of undocumented SX1262 register 0x8B5 on Heltec V4 and
Wireless Tracker V2 boards with the GC1109 FEM. This patch was
recommended by Heltec/Semtech and tested in MeshCore PR #1398, where
it significantly reduced packet loss on the Heltec V4.

* Use higher level function

* Add .venv/ to .gitignore
This commit is contained in:
Wessel
2026-02-21 16:08:14 +01:00
committed by GitHub
parent 8feb34e7a8
commit 9383d0bcfc
2 changed files with 12 additions and 0 deletions
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1
.gitignore vendored
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@@ -33,6 +33,7 @@ __pycache__
*~
venv/
.venv/
release/
.vscode/extensions.json
/compile_commands.json

11
src/mesh/SX126xInterface.cpp
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@@ -194,6 +194,17 @@ template <typename T> bool SX126xInterface<T>::init()
LOG_INFO("Set RX gain to power saving mode (boosted mode off); result: %d", result);
}
#ifdef USE_GC1109_PA
// Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity
// on boards with the GC1109 FEM. Sets bit 0 of register 0x8B5.
// Reference: https://github.com/meshcore-dev/MeshCore/pull/1398
if (module.SPIsetRegValue(0x8B5, 0x01, 0, 0) == RADIOLIB_ERR_NONE) {
LOG_INFO("Applied SX1262 register 0x8B5 patch for GC1109 RX improvement");
} else {
LOG_WARN("Failed to apply SX1262 register 0x8B5 patch for GC1109");
}
#endif
#if 0
// Read/write a register we are not using (only used for FSK mode) to test SPI comms
uint8_t crcLSB = 0;