mirror of
https://github.com/LMMS/lmms.git
synced 2026-05-29 09:18:34 -04:00
005b1a8e66
Makes the following changes to the Lb302 plugin for increased functionality, maintainability, and readability: - Add note velocity & note panning to Lb302 - Remove evil mutex+dynamic array combo in favor of a real-time safe ringbuffer queue - Use non-static data member initializers where possible - Use `std::numbers::pi` instead of `M_PI` - Use `std::array` and `std::unique_ptr` instead of manual memory management - Change plain-old-data classes with only public members to structs - Change some ints to f_cnt_t to better communicate their purpose and avoid weird implicit casting nonsense - Change floats to sample_t where appropriate to better communicate their purpose - Find suitable homes for loose constants - Prefix standard library math function calls with std:: - Ensure all floating-point literals intended to be floats end in 'f' and are not doubles to appease MSVC - Change uses of SIGNAL and SLOT macros to whatever they should be post-Qt6 upgrade - Tidy code to conform to current code conventions Also adds Hardware.h for low-level performance tools: - busyWaitHint(), supporting x86, ARM, and RISC-V - hardware_destructive_interference_size polyfill, supporting x86, ARM, RISC-V, and PPC - Moved the contents of denormals.h to Hardware.h, renamed disable_denormals() to disableDenormals() - Added ARM support to disableDenormals()
164 lines
6.7 KiB
C++
164 lines
6.7 KiB
C++
/*
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* Hardware.h - This file contains useful tools that are hardware-
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* dependent, such as cache-line size and busy-wait hints.
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*
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* Copyright (c) 2026 Fawn Sannar <rubiefawn/at/gmail.com>
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*
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* This file is part of LMMS - https://lmms.io
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef LMMS_HARDWARE_H
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#define LMMS_HARDWARE_H
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#include <cstdint>
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#include <new>
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#if __cpp_lib_hardware_interference_size >= 201703L
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#if defined(__GNUG__) && !defined(__clang__)
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// https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Winterference-size
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#pragma GCC diagnostic ignored "-Winterference-size"
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#endif
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#endif
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#include "lmmsconfig.h"
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#if defined(LMMS_HOST_X86_64) || defined(LMMS_HOST_X86)
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#include <immintrin.h>
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#elif defined(LMMS_HOST_ARM64) || defined(LMMS_HOST_ARM32)
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#if defined(__ARM_ACLE)
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#include <arm_acle.h>
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#elif defined(_MSC_VER)
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#include <intrin.h>
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#elif defined(__GNUG__) // HACK: Remove this once GCC properly provides __ARM_ACLE
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#if defined(LMMS_HOST_ARM64)
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// https://developer.arm.com/documentation/ddi0602/2026-03/Base-Instructions/ISB--Instruction-synchronization-barrier-
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// The parameter is ignored since 15 is the only valid value
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inline void __isb(unsigned int) { asm volatile ("isb 15" ::: "memory"); }
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#elif defined(LMMS_HOST_ARM32)
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inline void __yield() { asm volatile ("yield"); }
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#endif
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#endif
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#endif
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namespace lmms
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{
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//! @brief Platform-dependent minimum amount of padding between objects to prevent false cache sharing.
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//! @hideinitializer
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//! @see [`std::hardware_destructive_interference_size`](https://wg21.link/p0154)
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inline constexpr std::size_t hardware_destructive_interference_size =
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#if __cpp_lib_hardware_interference_size >= 201703L
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std::hardware_destructive_interference_size;
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#elif defined(LMMS_HOST_X86_64) || defined(LMMS_HOST_X86)
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64;
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#elif defined(LMMS_HOST_ARM64)
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256;
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#elif defined(LMMS_HOST_ARM32)
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64;
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#elif defined(LMMS_HOST_RISCV64) || defined(LMMS_HOST_RISCV32)
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64;
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#elif defined(LMMS_HOST_PPC64)
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128;
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#elif defined(LMMS_HOST_PPC32)
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32;
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#else
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64;
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#warning Defaulting to 64 for lmms::hardware_destructive_interference_size for this architecture. This may be incorrect.
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#endif
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//! @brief Platform-dependent hint to the processor that it is in a busy-wait loop.
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//! This helps optimize spinlocks by slowing down the processor a bit, which helps reduce contention on atomics.
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//! @see [x86-64 `pause`](https://www.felixcloutier.com/x86/pause)
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//! @see [ARM64 `isb`](https://developer.arm.com/documentation/ddi0602/2026-03/Base-Instructions/ISB--Instruction-synchronization-barrier-)
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//! (and [why it is used instead of `yield`](https://github.com/rust-lang/rust/commit/c064b6560b7ce0adeb9bbf5d7dcf12b1acb0c807))
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//! @see [ARM32 `yield`](https://developer.arm.com/documentation/ddi0597/2026-03/Base-Instructions/YIELD--Yield-hint-)
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//! @see [RISC-V `pause`](https://docs.riscv.org/reference/isa/unpriv/zihintpause.html)
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inline void busyWaitHint()
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{
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#if defined(LMMS_HOST_X86_64) || defined(LMMS_HOST_X86)
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_mm_pause();
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#elif defined(LMMS_HOST_ARM64)
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__isb(15);
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#elif defined(LMMS_HOST_ARM32)
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__yield();
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#elif defined(LMMS_HOST_RISCV64) || defined(LMMS_HOST_RISCV32)
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asm volatile ("pause");
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#else
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// TODO LMMS_HOST_PPC*
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#warning lmms::busyWaitHint() is not implemented on this architecture and will have no effect. Performance may suffer.
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#endif
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}
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//! @brief Disable IEEE 754 denormals on the current thread.
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//!
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//! This is desirable for audio calculations as processing denormal
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//! values is significantly slower than normal values, and in the
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//! context of audio signal processing, denormal values are typically
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//! near silence and contain no useful information anyways.
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inline void disableDenormals()
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{
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#if defined(LMMS_HOST_X86_64) || defined(LMMS_HOST_X86)
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// https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
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// Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture
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// 11.6.3 Checking for the DAZ Flag in the MXCSR Register
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unsigned int flags = 0x8000; // FTZ
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alignas(16) std::uint8_t buf[512] = {0};
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#if defined(LMMS_HOST_X86_64)
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_fxsave64(buf);
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#elif defined(LMMS_HOST_X86)
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_fxsave(buf);
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#endif
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flags |= buf[28] & 0x0040; // DAZ if supported
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_mm_setcsr(_mm_getcsr() | flags);
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#elif defined(LMMS_HOST_ARM64) || defined(LMMS_HOST_ARM32)
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constexpr auto FZ = 1 << 24; // Flushing denormalized numbers to zero control bit
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#if defined(_MSC_VER) && defined(LMMS_HOST_ARM64)
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// https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics
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// 0x5a20 == ARM64_SYSREG(0b11, 0b011, 0b0100, 0b0100, 0b000)
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_WriteStatusReg(0x5a20, _ReadStatusReg(0x5a20) | FZ);
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#elif defined(_MSC_VER) && defined(LMMS_HOST_ARM32)
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// https://learn.microsoft.com/en-us/windows/arm/arm32-to-arm64
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// https://learn.microsoft.com/en-us/windows/whats-new/deprecated-features
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#warning MSVC for ARM32 is deprecated. lmms::disableDenormals() is not implemented and will have no effect.
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#elif defined(LMMS_HOST_ARM64)
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// https://developer.arm.com/documentation/ddi0601/2026-03/AArch64-Registers/FPCR--Floating-point-Control-Register
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std::uint64_t fpcr;
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asm volatile ("mrs %0, fpcr" : "=r" (fpcr));
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asm volatile ("msr fpcr, %0" :: "ri" (fpcr | FZ));
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#elif defined(LMMS_HOST_ARM32)
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// https://developer.arm.com/documentation/ddi0601/2026-03/AArch32-Registers/FPSCR--Floating-Point-Status-and-Control-Register
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std::uint32_t fpscr;
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asm volatile ("vmrs %0, fpscr" : "=r" (fpscr));
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asm volatile ("vmsr fpscr, %0" :: "ri" (fpscr | FZ));
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#endif
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#else
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// TODO LMMS_HOST_RISCV*: https://docs.riscv.org/reference/isa/unpriv/f-st-ext.html
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// As of v2.2 of both the F and D extensions, there appears to be no
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// way to flush denormals to zero. This may change in the future.
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// TODO LMMS_HOST_PPC*: https://openpowerfoundation.org/specifications/isa
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// This is possible for SIMD instructions by setting bit 111 of the
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// VSCR register (a.k.a. the "NJ" flag), but there doesn't appear to
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// be an equivalent for scalar instructions?
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#warning lmms::disableDenormals() is not implemented on this architecture and will have no effect. Performance may suffer.
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#endif
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}
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} // namespace lmms
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#endif // LMMS_HARDWARE_H
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