Move the NextLevel AT into the TableMapper (descriptor-level) trait.
This allows us to provide a blanket implementation of TableMapperTable
for all tables where, Table::Descriptor : TableMapper.
Since the architectural details of descriptor implementation is hidden
behind traits, the code for walking page tables is arch-agnostic.
Therefore, promote it to shared code for use by other architectures.
Bit 7 on various descriptors in x86_64 can take on varying values
depending upon the descriptor type. Refelect that in the implementation
and fix a bug whereby the PAT bit would have been set when creating a
PTE.
The test harness code is useful across architectures. Therefore, move it
out of the arm64 directory so it can be used by other architectures
implementing paging unit-tests.
We currently define the MAP_SHIFT for a page-table level in two places,
`TableMapper` and `PgTable`. Store only one shift trait constant value
in the `PageTableEntry` trait.
Any traits which are architecture agnostic should be available to be
implemented by other architectures. Move them out from the arm64 module
into a non-architecure specific location.
Move PtePermissions to paging module which is feature-gated behind
`paging`.
Also move all AddressSpace related functionality behind the `proc_vm`
feature gate.
ptrace 'child' events are treated differently during a wait than
'normal' child events. Speciecially, a process that is being traced
receives events for all threads (all `Tid`s) from a process, rather than
the `Tgid`.
This fixes running strace on multi-threaded programs.
Make the `Tid` globally unique, rather than `Tgid` creating a new number
space. This allows ptrace to differentiate between threads when using
`-f` on a program which spawns threads.
If an object isn't aligned to a cache line boundary, the flush loop
advances by a full cache line stride from the misaligned start address.
This can cause the pointer to overshoot the object end before reaching
the next cache line, leaving it unflushed.
This was observed on secondary CPU bringup where the boot context struct
was not cache-line aligned, causing the secondary core to read stale
data from RAM for fields in the second cache line.
Fix this by aligning the start address down to a cache line boundary
before iterating.
Replace `CUR_TASK_PTR` with `ProcessCtx`. This allows differentiation
between functions that access process context (take in `ProcessCtx` as a
parameter) and those that don't.
When creating a new class of scheduleable tasks (softirqs, kthreads),
this ensure that those functions cannot call context-sensitive
functions.
Since a Arc<Work> can be obtained from `TASK_LIST`, this would allow the
potential mutation of 'owned'-state from other CPUs thereby causing a
race condition. Thefore, ensure that the deref of an `Arc<Work>` only
permits access to `t_shared`.
