Add support for latest Crucial Ballistix RGB RAM

The latest RAM modules all show up at address 0x27 instead of 0x20-0x23.
So lets remap them so they can be detected and controlled individually.
Since other RGB software can already handle them add and assign the
addresses used there as well.
This commit is contained in:
Mike Achtelik
2021-01-21 23:16:21 +01:00
committed by Adam Honse
parent d5336c9f36
commit e9107276cf

View File

@@ -8,13 +8,19 @@
#include <stdio.h>
#include <stdlib.h>
using namespace std::chrono_literals;
/*----------------------------------------------------------------------*\
| This list contains the available SMBus addresses for Crucial RAM |
\*----------------------------------------------------------------------*/
#define CRUCIAL_ADDRESS_COUNT 4
#define CRUCIAL_ADDRESS_COUNT 8
static const unsigned char crucial_addresses[] =
{
0x39,
0x3A,
0x3B,
0x3C,
0x20,
0x21,
0x22,
@@ -57,6 +63,15 @@ bool TestForCrucialController(i2c_smbus_interface* bus, unsigned char address)
} /* TestForCrucialController() */
void CrucialRegisterWrite(i2c_smbus_interface* bus, unsigned char dev, unsigned short reg, unsigned char val)
{
//Write Crucial register
bus->i2c_smbus_write_word_data(dev, 0x00, ((reg << 8) & 0xFF00) | ((reg >> 8) & 0x00FF));
//Write Crucial value
bus->i2c_smbus_write_byte_data(dev, 0x01, val);
}
/******************************************************************************************\
* *
* DetectCrucialControllers *
@@ -75,8 +90,44 @@ void DetectCrucialControllers(std::vector<i2c_smbus_interface*> &busses, std::ve
for (unsigned int bus = 0; bus < busses.size(); bus++)
{
int address_list_idx = -1;
IF_DRAM_SMBUS(busses[bus]->pci_vendor, busses[bus]->pci_device)
{
// Remap Crucial RAM modules on 0x27
for (unsigned int slot = 0; slot < 4; slot++)
{
int res = busses[bus]->i2c_smbus_write_quick(0x27, I2C_SMBUS_WRITE);
if (res < 0)
{
break;
}
do
{
address_list_idx++;
if(address_list_idx < CRUCIAL_ADDRESS_COUNT)
{
res = busses[bus]->i2c_smbus_write_quick(crucial_addresses[address_list_idx], I2C_SMBUS_WRITE);
}
else
{
break;
}
} while (res >= 0);
if(address_list_idx < CRUCIAL_ADDRESS_COUNT)
{
CrucialRegisterWrite(busses[bus], 0x27, 0x82EE, slot);
CrucialRegisterWrite(busses[bus], 0x27, 0x82EF, (crucial_addresses[address_list_idx] << 1));
CrucialRegisterWrite(busses[bus], 0x27, 0x82F0, 0xF0);
}
std::this_thread::sleep_for(1ms);
}
// Add Crucial controllers
for (unsigned int address_list_idx = 0; address_list_idx < CRUCIAL_ADDRESS_COUNT; address_list_idx++)
{